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3.8.2
%SA, %SB, and %SC References
Note: %SA, %SB, and %SC contacts are not set or reset until the input scan phase of the sweep
following the occurrence of the fault or a clearing of the fault table(s). %SA, %SB, and %SC
contacts can also be set or reset by user logic and CPU monitoring devices.
Reference System
Variable
%SA0001
#PB_SUM
%SA0002
#OV_SWP
%SA0003
#APL_FLT
%SA0009
#CFG_MM
%SA0008
#OVR_TMP
%SA0010
#HRD_CPU
%SA0011
#LOW_BAT
%SA0012
#LOS_RCK
%SA0013
#LOS_IOC
%SA0014
#LOS_IOM
%SA0015
#LOS_SIO
%SA0017
#ADD_RCK
%SA0018
#ADD_IOC
%SA0019
#ADD_IOM
%SA0020
#ADD_SIO
%SA0022
#IOC_FLT
%SA0023
#IOM_FLT
%SA0027
#HRD_SIO
GFK-2950C
Definition
Set when a checksum calculated on the application program does not match the
reference checksum. If the fault was due to a temporary failure, the condition can
be cleared by again storing the program to the CPU. If the fault was due to a hard
RAM failure, then the CPU must be replaced.
To clear this bit, clear the CPU fault table or power cycle the CPU.
Set when the CPU detects that the previous sweep took longer than the time
specified by the user. To clear this bit, clear the CPU fault table or power cycle the
CPU. Only occurs if the CPU is in Constant Sweep mode.
Set when an application fault occurs. To clear this bit, clear the CPU fault table or
power cycle the CPU.
Set when a configuration mismatch fault is logged in the fault tables. To clear this
bit, clear the CPU fault table or power cycle the CPU.
Set when the operating temperature of the CPU exceeds the normal operating
temperature, 58ºC. To clear this bit, clear the CPU fault table or power cycle the
CPU.
Set when the diagnostics detects a problem with the CPU hardware. To clear this
bit, clear the CPU fault table or power cycle the CPU.
The low battery indication is not supported for all CPU modules. For details, refer
Battery Status (Group 18)
to
The CPU may set this contact when an I/O module or special-purpose module has
reported a low battery. In this case, a fault will be reported in the I/O Fault Table.
To clear this bit, clear the CPU fault table or power cycle the CPU.
Set when an expansion rack stops communicating with the CPU. To clear this bit,
clear the CPU fault table or power cycle the CPU.
Set when a Bus Controller stops communicating with the CPU.
To clear this bit, clear the I/O Fault Table or power cycle the CPU.
Set when an I/O module stops communicating with the CPU.
To clear this bit, clear the I/O Fault Table or power cycle the CPU.
Set when an option module stops communicating with the CPU.
To clear this bit, clear the CPU fault table or power cycle the CPU.
Set when an expansion rack is added to the system.
To clear this bit, clear the CPU fault table or power cycle the CPU.
Set when a Bus Controller is added to a rack.
To clear this bit, clear the I/O Fault Table or power cycle the CPU.
Set when an I/O module is added to a rack.
To clear this bit, clear the I/O Fault Table or power cycle the CPU.
Set when an intelligent option module is added to a rack.
To clear this bit, clear the I/O Fault Table or power cycle the CPU.
Set when a Bus Controller reports a bus fault, a global memory fault, or an IOC
hardware fault. To clear this bit, clear the I/O Fault Table or power cycle the CPU.
Set when an I/O module reports a circuit or module fault.
To clear this bit, clear the I/O Fault Table or power cycle the CPU.
Set when a hardware failure is detected in an option module.
To clear this bit, clear the I/O Fault Table or power cycle the CPU.
February 2018
Chapter 3. Program Data
in Chapter 9.
47
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