Interrupts; Counters - Measurement Computing PCI-DAS64/M1/16 User Manual

PCI-DAS64/M1/16 User's Guide

Interrupts

Interrupts
Interrupt enable
ADC interrupt
DAC interrupt sources
(software-programmable)
External interrupt

Counters

User counter type
Configuration
Counter 1 source
Counter 1 gate
Counter 1 output
Clock input frequency
High pulse width
(clock input)
Low pulse width
(clock input)
Gate width high
Gate width low
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Table 14. Interrupt specifications
PCI INTA# - Mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9080
DAQ_ACTIVE:
DAQ_STOP:
DAQ_DONE:
DAQ_FIFO_1/4_FULL:
DAQ_SINGLE:
DAQ_EOSCAN:
DAQ_EOSEQ:
DAC_ACTIVE:
DAC_DONE:
DAC_FIFO_1/4_EMPTY:
DAC_HIGH_CHANNEL:
DAC_RETRANSMIT:
Interrupt is generated via edge-sensitive transition on the External Interrupt pin.
Rising/falling edge polarity software selectable.
Table 15. Counter specifications
82C54
One down counter, 16-bits. Counters 2 and 3 not used.
External, from connector (CTR1 CLK)
Available at connector (CTR1 GATE).
Available at connector (CTR1 OUT).
10 MHz max
30 nS min
50 nS min
50 nS min
50 nS min
0.8 V max
2.0 V min
0.4 V max
3.0 V min
6-9
Interrupt is generated when a DAQ sequence is active.
Interrupt is generated when A/D Stop Trigger In is detected.
Interrupt is generated when a DAQ sequence completes.
Interrupt is generated when ADC FIFO is ¼ full.
Interrupt is generated after each conversion completes.
Interrupt is generated after the last channel is converted in
multi-channel scans.
Interrupt is generated after each interval delay during multi-
channel scans.
Interrupt is generated when DAC waveform circuitry is active.
Interrupt is generated when a DAC sequence completes.
Interrupt is generated DAC FIFO is ¼ empty.
Interrupt is generated when the DAC high channel output is
updated.
Interrupt is generated when the end of a waveform sequence
has occurred in retransmit mode.
Specifications