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DRH0–DRH7: Destination register high-order 8 bits (FF84H, FF85H)
Used to set high-order 8 bits of dividends.
Set the low-order 4 bits of data to DRH0–DRH3 and the high-order 4 bits to DRH4–DRH7.
At the start of a multiplication (by writing "0" to FF86H•D0), the contents in this register are ignored.
After 10 CPU cycles (5 bus cycles) of multiplication process has finished, the high-order 8 bits of the
product are loaded in this register.
In a division process, data written to this register is loaded to the arithmetic circuit when an operation
starts (by writing "1" to FF86H•D0), and then a division is performed in 10 CPU clock cycles (5 bus
cycles). After the operation has finished, the remainder is loaded to this register. However, if an overflow
occurs in a division process, the remainder is not loaded and the high-order 8 bits of the dividend remains.
At initial reset, this register is undefined.
NF: Negative flag (FF86H•D3)
Indicates whether the operation result is a positive value or a negative value.
When "1" is read: Negative value (MSB of the results is "1")
When "0" is read: Positive value (MSB of the results is "0")
Writing: Invalid
NF is a read-only bit, so writing operation is invalid.
At initial reset, this flag is set to "0".
VF: Overflow flag (FF86H•D2)
Indicates whether an overflow has occurred or not in a division process.
When "1" is read: Overflow occurred
When "0" is read: Overflow has not occurred
Writing: Invalid
When a multiplication process has finished, this flag is always set to "0".
VF is a read-only bit, so writing operation is invalid.
At initial reset, this flag is set to "0".
ZF: Zero flag (FF86H•D1)
Indicates whether the operation result is zero or not.
When "1" is read: Zero
When "0" is read: Not zero
Writing: Invalid
ZF is a read-only bit, so writing operation is invalid.
At initial reset, this flag is set to "0".
CALMD: Calculation mode selection register/operation status (FF86H•D0)
Selects multiplication or division mode and starts operation.
When "1" is written: Selects/starts division
When "0" is written: Selects/starts multiplication
When "1" is read: Under operating
When "0" is read: Operation has finished
Writing to this register starts the specified operation. After that, this register is set to "1" and returns to "0"
when the multiplication or division process has finished.
At initial reset, this register is reset to "0".
4.13.6 Programming note
An operation process takes 10 CPU clock cycles (5 bus cycles) after writing to the calculation mode
selection register CALMD until the operation result is set to the destination register DRH/DRL and the
operation flags. While this operation is in process, do not read/write from/to the destination register
DRH/DRL and do not read NF/VF/ZF.
S1C63656 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Integer Multiplier)
EPSON
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