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FTRG1/FRUN1: Motor driver Ch. 1 pulse output trigger/status (FF10H•D0)
FTRG2/FRUN2: Motor driver Ch. 2 pulse output trigger/status (FF10H•D1)
This is the trigger bit to start a motor-drive pulse and the status bit.
• When writing
When "1" is written: Start outputting
When "0" is written: No operation
When writing has made, this bit functions as the trigger bit FTRGx (x = 1 or 2) to start outputting a
motor-drive pulse.
By writing "1" to FTRGx, the motor driver starts a motor-drive pulse output sequence for Ch. x.
No operation results when "0" is written to FTRGx.
• When reading
When "1" is read: RUN (during pulse output process)
When "0" is read: STOP (idle status)
When reading this bit functions as the status bit FRUNx (x = 1 or 2) that indicates the motor driver status.
After "1" is written to FTRGx (this bit), the motor driver starts a motor-drive pulse output sequence
within 0.2 msec when PFTYP = "1" or within 1.0 msec when PFTYP = "0". At this point FRUNx is set to "1"
and is cleared to "0" upon completion of the pulse output sequence. In other words, this bit set to "1"
indicates that the motor driver is in busy status for pulse output process.
Writing "1" to FTRGx for trigger is ignored while FRUNx is set to "1".
At initial reset, this bit is set to "0".
PFWA0–PFWA4: Motor driver Ch. 1 pulse width select register (FF12H, FF11H•D0)
PFWB0–PFWB4: Motor driver Ch. 2 pulse width select register (FF14H, FF13H•D0)
Selects the motor-drive pulse width. The selectable range is changed according to the selection of the
pulse width base clock register PFTYP.
PFWA4
PFWB4
At initial reset, these registers are set to "00H".
S1C63656 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stepping Motor Driver)
Table 4.15.5.2 Setting up the motor-drive pulse
PFWA3
PFWA2
PFWA1
PFWB3
PFWB2
PFWB1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
X
X
PFWA0
Pulse width
PFWB0
PFTYP = "1"
1.46 msec
0
1.71 msec
1
1.95 msec
0
2.20 msec
1
2.44 msec
0
2.69 msec
1
2.93 msec
0
3.17 msec
1
3.42 msec
0
3.66 msec
1
3.91 msec
0
4.15 msec
1
4.40 msec
0
4.64 msec
1
4.88 msec
0
5.13 msec
1
5.37 msec
0
5.62 msec
1
5.86 msec
0
6.10 msec
1
6.35 msec
0
6.59 msec
1
6.84 msec
0
7.08 msec
1
3.42 msec
X
EPSON
PFTYP = "0"
11.72 msec
13.67 msec
15.63 msec
17.58 msec
19.53 msec
21.48 msec
23.44 msec
25.39 msec
27.34 msec
29.30 msec
31.25 msec
33.20 msec
35.16 msec
37.11 msec
39.06 msec
41.02 msec
42.97 msec
44.92 msec
46.88 msec
48.83 msec
50.78 msec
52.73 msec
54.69 msec
56.64 msec
27.34 msec
125
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