Epson S1C63656 Technical Manual page 91

PTPS00, PTPS01: Timer 0 prescaler division ratio selection register (FFC3H•D2, D3)
PTPS10, PTPS11: Timer 1 prescaler division ratio selection register (FFC4H•D2, D3)
Sets the division ratio of the prescaler as shown in Table 4.10.10.2.
When the event counter mode is selected to timer 0, the setting of PTPS00 and PTPS01 becomes invalid.
When timers 0 and 1 are used as a 16-bit timer, the setting of PTPS10 and PTPS11 becomes invalid.
At initial reset, these registers are set to "0".
MOD16: 16-bit mode selection register (FFC0H•D3)
Selects whether timers 0 and 1 are used as a 16-bit timer or 2 channels of 8-bit timer.
When "1" is written: 16-bit timer
When "0" is written: 8-bit timer
Reading: Valid
When "1" is written to MOD16, a 16-bit timer is configured with timer 0 for low-order byte and timer 1 for
high-order byte. Use the timer 0 registers for control. When "0" is written to MOD16, timer 0 and timer 1
are used as independent 8-bit timers.
At initial reset, this register is set to "0".
EVCNT: Timer 0 counter mode selection register (FFC0H•D2)
Selects a counter mode for timer 0.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading: Valid
The counter mode for timer 0 is selected from either the event counter mode or timer mode. When "1" is
written to the EVCNT register, the event counter mode is selected and when "0" is written, the timer
mode is selected.
At initial reset, this register is set to "0".
FCSEL: Timer 0 function selection register (FFC0H•D1)
Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode.
When "1" is written: With noise rejector
When "0" is written: Without noise rejector
Reading: Valid
When "1" is written to the FCSEL register, the noise rejector is used and counting is done by an external
clock (K13) with 0.98 msec* or more pulse width. The noise rejector allows the counter to input the clock
at the second falling edge of the internal 2,048 Hz* signal after changing the input level of the K13 input
port terminal. Consequently, the pulse width of noise that can reliably be rejected is 0.48 msec* or less.
(∗: f = 32.768 kHz)
OSC1
When "0" is written to the FCSEL register, the noise rejector is not used and the counting is done directly
by an external clock input to the K13 input port terminal.
Setting of this register is effective only when timer 0 is used in the event counter mode.
At initial reset, this register is set to "0".
S1C63656 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Table 4.10.10.2 Selection of prescaler division ratio
PTPSx1 PTPSx0
1 1
1 0
0 1
0 0
EPSON
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
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