Interrupt Control Register (Interrupt From Board To Pc) - Omron 3G8F7-CRM21 User Manual

PCI Register Specifications
B-2-5

Interrupt Control Register (Interrupt from Board to PC)

Flags of "Interrupt
from Board to PC"
Interrupt Mask (Offset
0x0004)
bit7
Flag BD_WDT
Access rule R/W
Initial value 0
This register is used to control interrupts from the Board to the PC.
The Interrupt Mask register is used to specify the generation of an interrupt by
a certain cause. The cause that is 1 in the Interrupt Mask register will
generate an interrupt. The applicable flag in the Interrupt Mask register must
be set to 0 when you want to confirm the cause not by an interrupt but by
polling.
When an interrupt occurs, the interrupt cause can be confirmed in the
Interrupt Cause Indication register.
The cause of the interrupt can be cleared by setting the relevant flag in the
Interrupt Clear register to 1. When all interrupt causes are cleared, the
interrupt itself is cleared.
Flag
CMD_ACK
BD_SND
SND_ACK
REQ_RES
Reserved
INIEND
REQ_ACC_ACK
BD_WDT
bit6 bit5
REQ_ACC INIEND
_ACK
R/W R/W
0 0
Bit
0 The acknowledgment made by the Board against the
command request made by the PC to the Board
1 Used when the Board notifies the PC of an event
transmission
2 The acknowledgment made by the Board against the
event transmission request made by PC to the Board
3 Used when the Board requests the PC of a Board
reset
4
5 The Board notifies the PC that the firmware
initialization has been completed.
The completion cause is stored in the Initialization
completion notification of the shared memory area.
6 The acknowledgment made by the Board against the
cyclic area access right request made by the PC to
the Board (a notification that the access right has
been successfully obtained)
7 The interrupt cause that is generated when the
Board WDT times out
bit4 bit3
Unused REQ_RES SND_ACK
R/W R/W
0 0
Section B-2
Description
-
bit2 bit1
BD_SND CMD_ACK
R/W R/W
0 0
bit0
R/W
0
105