Omron 3G8F7-CRM21 User Manual page 166

Componet master board for pci bus/ compactpci bus
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Command Specifications
Command
REQUEST_RESETSTATUS
Purpose
Code
Argument
Response code
Remarks
Command
SET_PC_WDT
Purpose
Code
Argument
Response code
Remarks
146
Issue a request to clear the Detailed status group.
0x2002
Clearing status 1-WORD data,
items
Set the bits to clear to 1 (ON) and the bits not to clear to 0
(OFF).
Bit
0 to 4
Reserved area, Set 0 (OFF).
5
Master status
6
Error counter
7 to 10
Reserved area, Set 0 (OFF).
11
Error log
12 to 15
Reserved area, Set 0 (OFF).
Normal end: 0x0000
It is cleared at the time a normal end is the response.
When the Master status is set to be cleared, the Maximum communication
cycle time, the Cumulative CRC reception error and the Cumulative code
reception error in the Master status are cleared.
Set the PC Watchdog Timer.
0x3001
Timer value
1-WORD data,
Unit: 10 ms
Range: 0x0000, 0x0001 to 0xFFFF (1 to 655350 ms)
(Setting 0x0000 will disable the PC WDT function.)
Normal end: 0x0000
When the PC WDT is enabled, be sure to refresh it before it times out.
See Section 5-5 for the usage of PC WDT.
Flag name
Section B-4

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