Analog Devices ADV7511W Hardware User's Manual page 5

ADV7511W
TABLE OF FIGURES
Figure 1 ADV7511W Functional Block Diagram....................................................................................................................................... 10
Figure 2 Timing for Video Data Interface ................................................................................................................................................... 13
Figure 3 Timing for I2S Audio Interface ..................................................................................................................................................... 13
Figure 4 Timing for S/PDIF Audio Interface .............................................................................................................................................. 14
Figure 5 64-lead LQFP configuration (top view - not to scale) ................................................................................................................ 16
Figure 6 64-lead Low-Profile Quad Flat Pack [LQFP-SW64-2] ............................................................................................................... 19
Figure 7 2X Clock timing ............................................................................................................................................................................... 23
Figure 8 DDR DE timing - Register 0x16[1] = 1 ......................................................................................................................................... 26
Figure 9 DDR DE timing - Register 0x16[1] = 0 ......................................................................................................................................... 26
Figure 10 I2S Standard Audio - Data width 16 to 24 bits per channel .................................................................................................. 28
Figure 11 I2S Standard Audio - 16-bit samples only ............................................................................................................................... 29
Figure 12 Serial Audio - Right-Justified .................................................................................................................................................... 29
Figure 13 Serial Audio - Left-Justified ....................................................................................................................................................... 29
Figure 14 AES3 Direct Audio ...................................................................................................................................................................... 30
Figure 15 S/PDIF Data Timing .................................................................................................................................................................... 30
Figure 16 Typical All-HDMI Home Theatre ............................................................................................................................................. 32
Figure 17 Sync Processing Block Diagram ................................................................................................................................................ 34
Figure 18 Single Channel of CSC (In_A) ................................................................................................................................................... 35
Figure 19 Serial Port Read/Write Timing .................................................................................................................................................. 38
Figure 20 Serial Interface-Typical Byte Transfer .................................................................................................................................... 39
Figure 21 Power Supply Domains ............................................................................................................................................................... 39
Figure 22 AVDD and PVDD Max Noise vs. Frequency .......................................................................................................................... 41
Figure 23 LC Filter Transfer Curve ............................................................................................................................................................ 42
Figure 24 CEC external connection ............................................................................................................................................................ 43
Figure 25 Example Schematic ...................................................................................................................................................................... 44
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HARDWARE USER'S GUIDE
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