Table 3 Complete Pinout List Adv7511W - Analog Devices ADV7511W Hardware User's Manual

ADV7511W
Complete Pinout List ADV7511W
Table 3
Pin No. Mnemonic
37 to 44, D[23:0]
45 to 50, 52, 54
55 to 62
53 CLK
63 DE
64 HSYNC
2 VSYNC
14 R_EXT
30 HPD
3 S/PDIF
4 MCLK
2
8-5 I S[3:0]
9 SCLK
10 LRCLK
22 PD/AD
17, 18 TxC−/TxC+
26, 27 Tx2−/Tx2+
23, 24 Tx1−/Tx1+
20, 21 Tx0−/Tx0+
28 INT
15, 19, 25 AVDD
1, 11, 31, 51 DVDD
12 PVDD
13 BGVDD
29 DVDD_3V
PAD GND
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Type Description
I
Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic
levels from1.8V up to 3.3V. See ▶Figure 2 for timing details.
I Video Clock Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
I Data Enable signal input for Digital Video. Supports typical CMOS logic levels from
1.8V up to 3.3V.
I Horizontal Sync Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
I Vertical Sync Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
I Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this
pin and ground.
I Hot Plug Detect signal input. This indicates to the interface whether the sink is
connected. 1.8V to 5.0 V CMOS logic level.
I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This pin is typically used as
the audio input from a Sony/Philips digital interface. Supports typical CMOS logic
levels from 1.8V up to 3.3V. See ▶ Figure 4 for timing details.
I MCLK input for SPDIF and I2S audio. (See ▷ADV7511 Programming Guide for
details on the register bit that controls this). .Supports typical CMOS logic levels
from 1.8V up to 3.3V.
2
I I S Audio Data Inputs. These represent the eight channels of audio (two per
input) available through I
3.3V. See Figure 3 for timing details.
2
I I S Audio Clock input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
I Left/Right Channel signal input. Supports typical CMOS logic levels from1.8V up to
3.3V.
I Power-Down Control and I
polarity are set by the PD/AD pin state when the supplies are applied to the
ADV7511W. Supports typical CMOS logic levels from 1.8V up to 3.3V.
O Differential TMDS Clock Output. Differential clock output at pixel clock rate;
TMDS logic level.
O Differential TMDS Output Channel 2. Differential output of the red data at 10×
the pixel clock rate; TMDS logic level.
O Differential TMDS Output Channel 1. Differential output of the green data at 10×
the pixel clock rate; TMDS logic level.
O Differential TMDS Output Channel 0. Differential output of the blue data at 10×
the pixel clock rate; TMDS logic level.
O Interrupt signal output. CMOS logic level. A 2 kΩ pull-up resistor (10%) to
interrupt the microcontroller IO supply is recommended.
P 1.8V Power Supply for TMDS Outputs.
P 1.8V Power Supply for Digital and I/O Power Supply. These pins supply power to
the digital logic and I/Os. They should be filtered and as quiet as possible.
P 1.8V PLL Power Supply. The most sensitive portion of the ADV7511W is the clock
generation circuitry. This pin provide power to the PLL clock. The designer
should provide quiet, noise-free power to these pins.
P Band Gap Vdd.
P 3.3V Power Supply.
P Ground. The ground return for all circuitry on-chip. It is recommended that the
ADV7511W be assembled on a single, solid ground plane with careful attention
given to ground current paths.
2
S. Supports typical CMOS logic levels from 1.8V up to
2 2
C Address Selection. The I C address and the PD
HARDWARE USER'S GUIDE
Rev. A
Rev A