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Summary of Contents for Analog Devices ADV7511W
- Page 1 ADV7511W Low-Power HDMI 1.4a Transmitter HARDWARE USER’S GUIDE - Revision A – July 2011 Rev A Page 1 of 45...
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Page 2: Revision History
ADV7511W HARDWARE USER’S GUIDE Rev.A REVISION HISTORY Rev. 0: Initial Release 4/11 Rev A: Section Change Description Corrected register bit information for the “Input ID” bits Section ▶ 6.1.2 Corrected Mux select bit table Figure 17 Rev A Page 2... -
Page 3: Table Of Contents
ADV7511W HARDWARE USER’S GUIDE Rev. A TABLE OF CONTENTS Section 1: Introduction ......................................7 Scope and Organization ..................................7 1.1.1 Links ........................................ 7 1.1.2 Symbols ......................................7 1.1.3 Format Standards ................................... 7 ... - Page 4 ADV7511W HARDWARE USER’S GUIDE Rev.A 6.4.4 4:2:2 to 4:4:4 and 4:4:4 to 4:2:2 Conversion Block ........................36 DDC Controller ....................................36 Inter-IC Communications (I2C) ..............................36 6.6.1 Two-Wire Serial Control Port ..............................36 ...
- Page 5 ADV7511W HARDWARE USER’S GUIDE Rev. A TABLE OF FIGURES Figure 1 ADV7511W Functional Block Diagram............................10 Figure 2 Timing for Video Data Interface ..............................13 Figure 3 Timing for I2S Audio Interface ..............................13 ...
- Page 6 Electrical Specifications .................................. 11 Table 2 Absolute Maximum Ratings ................................14 Table 3 Complete Pinout List ADV7511W ............................... 17 Table 4 Input ID Selection ................................... 20 Table 5 Normal RGB or YCbCr 4:4:4 (24 bits) with Separate Syncs; Input ID = 0 ................21 ...
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Page 7: Section 1: Introduction
SECTION 1: INTRODUCTION Scope and Organization This document is intended to help the hardware designer understand what is necessary to design for the ADV7511W and maintain the highest levels of performance. The ADV7511W Hardware User's Guide (HUG) provides guidelines to design the schematics and board layout. -
Page 8: Overview
Rev.A Overview The ADV7511W is a high speed High Definition Multimedia Interface (HDMI) transmitter that is capable of supporting an input data rate up to 165MHz (1080p @ 60Hz, UXGA @ 60Hz). Careful hardware design (schematics and PCB layout) is recommended to optimize the performance and to ensure HDMI compliance. -
Page 9: Section 2: Reference Documents
ADV7511W HARDWARE USER’S GUIDE Rev. A SECTION 2: REFERENCE DOCUMENTS ADI Documents ADV7511W Data Sheet ADV7511W Programming Guide AN-810 - EDID/HDCP Controller Application Note Industry Specifications EIA/CEA-861-E HDMI Specification 1.4a HDCP 1.4 Rev A Page 9 of 45... -
Page 10: Section 3: Block Diagram
ADV7511W HARDWARE USER’S GUIDE Rev.A SECTION 3: BLOCK DIAGRAM ADV7511W Functional Block Diagram Figure 1 CEC CONTROLLER/ BUFFER CEC_CLK HDCP KEYS SPDIF I2S[3:0] HDCP AUDIO MCLK ENCRYPTION DATA CAPTURE 4:2:2 LRCLK SCLK 4:4:4 COLOR D[23:0] TX0+/TX0– SPACE VSYNC VIDEO CONVERTER... -
Page 11: Section 4: Specifications
ADV7511W HARDWARE USER’S GUIDE Rev. A SECTION 4: SPECIFICATIONS Electrical Specifications Table 1 ADV7511W Parameter Conditions Temp Test Level Unit DIGITAL INPUTS Data Inputs – Video, Audio and CEC_CLK Input Voltage, High (V Full 1.35 Input Voltage, Low (V Full -0.3... - Page 12 ADV7511W HARDWARE USER’S GUIDE Rev.A ADV7511W Parameter Conditions Temp Test Level Unit AC SPECIFICATIONS TMDS Output Clock Frequency 25°C TMDS Output Clock Duty Cycle 25°C Input Video Clock Frequency Full Input Video Data Setup Time – t Full Input Video Data Hold Time – t...
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Page 13: Figure 2 Timing For Video Data Interface
ADV7511W HARDWARE USER’S GUIDE Rev. A Timing for Video Data Interface Figure 2 Rising Edge VHLD Input data: D(23:0), DE, Valid Data HSYNC, VSYNC VHLD VHLD Dual Edge Input DDR data: D(23:0), DE, Valid Data Valid Data HSYNC, VSYNC Timing for I2S Audio Interface... -
Page 14: Figure 4 Timing For S/Pdif Audio Interface
ADV7511W HARDWARE USER’S GUIDE Rev.A Timing for S/PDIF Audio Interface Figure 4 MCLK Rising Edge R0x0B[6] = 0 AHLD Audio data: Valid data S/PDIF MCLK AHLD Falling Edge R0x0B[6] = 1 Audio data: Valid data S/PDIF Absolute Maximum Ratings Table 2... -
Page 15: Explanation Of Test Levels
ADV7511W HARDWARE USER’S GUIDE Rev. A Explanation of Test Levels 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. -
Page 16: Section 5: Pin And Package Information
Rev.A SECTION 5: PIN AND PACKAGE INFORMATION This section shows the pinout of the ADV7511W 64-lead LQFP package. This section also contains a brief description of the different pins as well as the mechanical drawings 64-lead LQFP configuration (top view - not to scale) -
Page 17: Table 3 Complete Pinout List Adv7511W
I/Os. They should be filtered and as quiet as possible. PVDD 1.8V PLL Power Supply. The most sensitive portion of the ADV7511W is the clock generation circuitry. This pin provide power to the PLL clock. The designer should provide quiet, noise-free power to these pins. - Page 18 ADV7511W HARDWARE USER’S GUIDE Rev.A Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8V to 3.3V. Serial Port Data Clock input. This pin serves as the serial port data clock slave for register access.
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Page 19: Mechanical Drawings And Outline Dimensions
ADV7511W HARDWARE USER’S GUIDE Rev. A Mechanical Drawings and Outline Dimensions 64-lead Low-Profile Quad Flat Pack [LQFP-SW64-2] Figure 6 12.20 12.00 SQ 1.60 10.20 11.80 10.00 SQ 0.75 9.80 0.60 0.45 1.00 REF PIN 1 SEATING PLANE EXPOSED 5.10 5.00 SQ 4.90... -
Page 20: Section 6: Functional Description
6.1.2 The ADV7511W can accept video data from as few as eight pins (either YCbCr 4:2:2 double data rate [DDR] or YCbCr 4:2:2 with 2x pixel clock) to as many as 24 pins (RGB 4:4:4 or YCbCr 4:4:4). In addition it can accept HSYNC, VSYNC and DE (Data Enable). -
Page 21: Table 5 Normal Rgb Or Ycbcr 4:4:4 (24 Bits) With Separate Syncs; Input Id = 0
ADV7511W HARDWARE USER’S GUIDE Rev. A Normal RGB or YCbCr 4:4:4 (24 bits) with Separate Syncs; Input ID = 0 Table 5 Input Data<23:0> Format RGB 444 R[7:0] G[7:0] B[7:0] YCbCr 444 Cr[7:0] Y[7:0] Cb[7:0] An input format of RGB 4:4:4 or YCbCr 4:4:4 can be selected by setting the input ID (R0x15[3:0]) to 0. There is no need to set the Input Style (R0x16[3:2]). -
Page 22: Table 6 Ycbcr 4:2:2 Formats (24, 20, Or 16 Bits) Input Data Mapping: 0X48[4:3]='00' (Evenly Distributed) Input Id=1 Or 2
ADV7511W HARDWARE USER’S GUIDE Rev.A YCbCr 4:2:2 Formats (24, 20, or 16 bits) Input Data Mapping: Table 6 0x48[4:3]=‘00’ (evenly distributed) Input ID=1 or 2 Input Data<23:0> Format Style 1 YCbCr422 Cb[11:4] Y[11:4] Cb[3:0] Y[3:0] Sep. Sync Cr[11:4] Y[11:4] Cr[3:0]... -
Page 23: Figure 7 2X Clock Timing
Input ID=7: This input format is the same as input ID 3 with the exception that the clock is not 2X the pixel rate, but is double data rate (DDR) Figure 8 and the Input ID (R0x15[3:0]) is set to 0x7. For timing details, see the ▷ ADV7511W Hardware User’s Guide and ▶ and ▶ Figure . -
Page 24: Table 8 Ycbcr 4:2:2 (8 Bits) Ddr With Separate Syncs: Input Id = 6, Right Justified (R0X48[4:3] = '01')
ADV7511W HARDWARE USER’S GUIDE Rev.A YCbCr 4:2:2 (8 bits) DDR with Separate Syncs: Input ID = 6, right justified (R0x48[4:3] = ‘01’) Table 8 Input Format Data<23:0> Style 1 YCrCB 422 Sep. Cb[3:0] Y[3:0] Syncs (DDR) Cb[7:4] Y[7:4] 8 bit... -
Page 25: Table 10 Ycbcr 4:2:2 (12, 10, 8 Bits) Ddr With Separate Syncs:input Id = 6, Evenly Distributed (R0X48[4:3] = '00')
ADV7511W HARDWARE USER’S GUIDE Rev. A YCbCr 4:2:2 (12, 10, 8 bits) DDR with Separate Syncs:Input ID = 6, evenly distributed (R0x48[4:3] = ‘00’) Table 10 Input Format Data<23:0> Style 1 YCrCb422 Sep Y[7:4] Cb[3:0] Y[3:0] Syncs (DDR) Cb[11:8] Cb[7:4]... -
Page 26: Audio Data Capture Block
AES3 stream formats. The Audio Data Capture Block captures the audio samples and converts them into audio packets which are sent through the HDMI link (if the ADV7511W is set in HDMI mode). Please refer to the ADV7511 Programming Guide for more information. -
Page 27: Table 11 Audio Input Format Summary
ADV7511W HARDWARE USER’S GUIDE Rev. A Table 11 illustrates the many audio input and output options that are available with the ADV7511W. Note ‘required’ and ‘optional’ clock notations. Audio input format summary Table 11 Input Output Audio Audio I2S Format... -
Page 28: Inter-Ic Sound (I2S) Audio
R0x0C[1:0] and sample word lengths between 16 bits and 24 bits (R0x14[3:0]). If the I2S data changes on the rising clock edge it is recommended that it be latched into the ADV7511W on the falling edge. If the I2S data changes on the falling clock edge, it is recommended that it be latched into the ADV7511W on the rising edge. -
Page 29: Figure 11 I2S Standard Audio - 16-Bit Samples Only
ADV7511W HARDWARE USER’S GUIDE Rev. A I2S Standard Audio – 16-bit samples only Figure 11 LRCLK LEFT RIGHT SCLK I2S[3:0] left left right right 16 Clock Slots 16 Clock Slots I2S Standard 16-bit per channel R0x0C[1:0] = ‘00’ Serial Audio – Right-Justified... -
Page 30: Sony/Philips Digital Interface (S/Pdif)
The ADV7511W is capable of accepting two-channel linear pulse code modulation (LPCM) and encoded audio up to a 192KHz sampling rate via the S/PDIF. S/PDIF audio input is selected by setting R0x0A[4] = ‘1’ . The ADV7511W is capable of input. -
Page 31: Input Voltage Tolerance
0x72 and the power down will be active high. If the PD/AD pin is high (when the supplies are turned on), the device address will be 0x7A and the power down will be active low. The ADV7511W power state can also be controlled via I2C registers (the PD pin and PD register bit are “or’ed”... -
Page 32: Interrupt Output (Int)
PLL Circuit 6.2.5 The phase-locked loop (PLL) generates the TMDS output clock as well as clocks used internally by the ADV7511W to serialize the data. The PLL filters high-frequency jitter components to minimize the output data clock jitter. Consumer Electronic Control (CEC) Unused Inputs 6.3.1... -
Page 33: Video Data Formatting
When transmitting video data across the TMDS interface, it is necessary to have an Hsync, Vsync, and Data Enable (DE) defined for the image. There are three methods for sync input to the ADV7511W. See ▶ Figure 17 for a block diagram of the sync processing capabilities. -
Page 34: Color Space Conversion (Csc) Matrix
0x34 0x17[6:5] generation in the embedded sync decoder section. The ADV7511W will use the signal generated by the EAV and SAV as the DE by default, but a new DE can also be generated. Sync adjustment is also available. ▷ Refer to the ADV7511 Programming Guide for details on how to program the DE and sync generator when embedded syncs are used. -
Page 35: Figure 18 Single Channel Of Csc (In_A)
ADV7511W HARDWARE USER’S GUIDE Rev. A separate coefficients. In each CSC channel, the order of input remains the same – Out_A will have the same input (In_A, In_B, In_C) as Out_B and Out_C. The coefficients will be different for each channel. Also included is an offset value for each row of the matrix and a scaling multiple for all values. -
Page 36: 4:2:2 To 4:4:4 And 4:4:4 To 4:2:2 Conversion Block
The 4:2:2 to 4:4:4 conversion block can convert 4:2:2 input signals into the 4:4:4 timing format. This is necessary, for instance, if the ADV7511W is set in DVI mode and has 4:2:2 format as its video input. The ADV7511W is also capable of performing 4:4:4 to 4:2:2 conversions. -
Page 37: Data Transfer Via I2C
If the transmitted slave address matches the address of the device (set by the state of the A2 input pin as shown in ▶Table 16), the ADV7511W acknowledges by bringing SDA low on the 9th SCL pulse. If the addresses do not match, the ADV7511W does not acknowledge. -
Page 38: Serial Interface Read/Write Examples
ADV7511W HARDWARE USER’S GUIDE Rev.A Serial Port Read/Write Timing Figure 19 BUFF STOSU STASU STAH Serial Interface Read/Write Examples 6.6.3 Write to one control register: ■ Start signal ■ Slave address byte (R/ W bit = low) ■ Base address byte ■... -
Page 39: Power Domains
Power Domains All power domains of the ADV7511W operate off of 1.8 volts, with the exception of the DVDD_3V which is 3.3 volts. It is recommended that the ADV7511W has its own designated 1.8V linear regulator and that the PVDD, AVDD and DVDD PCB power domains be segregated using inductors as illustrated in ▶... -
Page 40: Power Supply Sequencing
In Section 4: the specifications table lists the maximum power as 326mW at 1080p, CSC off. ▶ Table 17illustrates the maximum power consumed by individual circuits in the ADV7511W. All of these entries are for worst case operations – 1080p output, and 192KHz audio sampling frequency. -
Page 41: Section 7: Pcb Layout Recommendations
▶Figure 21. An LC filter on the output of the power supply is recommended to attenuate the noise and should be placed as close to the ADV7511W as possible. An effective LC filter for this is a 10 μH inductor and a 10μF capacitor (see▶... -
Page 42: Video Clock And Data Inputs
ADV7511W HARDWARE USER’S GUIDE Rev.A LC Filter Transfer Curve Figure 23 Video Clock and Data Inputs Any noise that that is coupled onto the CLK input trace will add jitter to the system. It is a recommended to control the impedance of the CLK trace. -
Page 43: Current Reference Pin: R_Ext
ADV7511W HARDWARE USER’S GUIDE Rev. A Current Reference Pin: R_EXT The external reference resistor should be connected between the R_EXT pin and ground with as short a trace as possible. The external reference resistor must have a value of 887 Ohms (+/-1% tolerance). It is strongly recommended to avoid running any high-speed AC or noisy signals next to the R_EXT line or close to it. -
Page 44: Figure 25 Example Schematic
ADV7511W HARDWARE USER’S GUIDE Rev.A Example Schematic Figure 25 1.8V 3.3V Leakage < 1.8uA Interrupt to processor CEC osc. CEC_CLK 1.8V DDCSDA DDCSCL ADV7511W Video data HDMI data Audio data R_EXT 887 ohms 1% Rev A Page 44 of 45... -
Page 45: Section 8: Glossary
Inter-IC Sound is a serial Philips bus designed specifically for audio. LPCM Linear Pulse-Code Modulation is a method of encoding audio samples. Low-Profile Quad Flat Pack is the type of package for the ADV7511W. LQFP Phase-Locked Loop. Red Green Blue is the standard definition for three-color graphics and video.
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