ADV7511W
Parameter
AC SPECIFICATIONS
TMDS Output Clock Frequency
TMDS Output Clock Duty Cycle
Input Video Clock Frequency
Input Video Data Setup Time – t
Input Video Data Hold Time – t
TMDS Differential Swing
Differential Output Timing
Low-to-High Transition Time
High-to-Low Transition Time
V
and H
Delay from DE Falling
SYNC
SYNC
Edge
V
and H
Delay to DE Rising
SYNC
SYNC
Edge
AUDIO AC TIMING (see ▶ Figure 3 to
▶ Figure 4
SCLK Duty Cycle See ▶ Table 12
When N/2 = even number
When N/2 = odd number
2
I
S[3:0], S/PDIF, LRCLK Setup – t
2
I
S[3:0], S/PDIF, LRCLK Hold Time –
t
AHLD
CEC
CEC_CLK Frequency
CEC_CLK Accuracy
I2C Interface (see ▶Figure 19)
SCL Clock Frequency
SDA Setup Time - t
DSU
SDA Hold Time – t
DHO
Setup for Start – t
STASU
Hold Time for Start – t
STAH
Setup for Stop – t
STOSU
1.
See Explanation of Test Levels section.
2.
This is measured at 0.9V. The relationship between clock and data is programmable in 400ps steps
3.
UI = unit interval.
4.
12MHz crystal oscillator for default register settings.
I2C data rates of 100KHz and 400KHz supported.
Page 12
of 45
Conditions
2
VSU
2
VHLD
ASU
1
Temp
Test Level
25°C
IV
25°C
IV
Full
Full
IV
Full
IV
25°C
VII
25°C
VII
25°C
VII
25°C
IV
25°C
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
VIII
Full
VIII
Full
Full
Full
Full
Full
Full
HARDWARE USER'S GUIDE
ADV7511W
Min
Typ
Max
20
165
48
52
165
1.8
1.3
900
1100
1200
75
95
75
95
1
1
40
50
60
49
50
51
2
2
4
3
12
100
-2
+2
400
100
100
0.6
0.6
0.6
Rev.A
Unit
MHz
%
MHz
nS
nS
mV
pS
pS
3
UI
UI
%
%
nS
nS
MHz
%
kHz
nS
nS
uS
uS
uS
Rev A
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