Input Voltage Tolerance; Output Connections; Output Formats Supported; Tmds Outputs - Analog Devices ADV7511W Hardware User's Manual

ADV7511W
device address will be 0x72 and the power down will be active high. If the PD/AD pin is high (when the supplies are
turned on), the device address will be 0x7A and the power down will be active low. The ADV7511W power state can
also be controlled via I2C registers (the PD pin and PD register bit are "or'ed" together). For further information,
please refer to the Power Management section of the ADV7511 Programming Guide.

Input Voltage Tolerance

6.1.6
The digital inputs (video, audio) on the ADV7511W work with 1.8V and 3.3V signal levels. The I2C ports
(DDCSDA/DDCSCL and SDA/SCL) and (Consumer Electronic Control) CEC port work with 1.8V and 3.3V and are
tolerant of 5V logic levels.

Output Connections

6.2

Output Formats Supported

6.2.1
The ADV7511W supports the following output formats:
■ 24 bit RGB 4:4:4
■ 24 bit YCbCr 4:4:4
■ 24 bit YCbCr 4:2:2

TMDS Outputs

6.2.2
The three TMDS output data channels have signals which can run up to 1.5GHz. It is highly recommended to match
the length of the traces in order to minimize the following:
Intra-pair skew (skew between + and - )
Inter-pair skew (skew between Channels 0, 1, and 2 and Clock)
The traces should also have a 50 Ohm transmission line impedance characteristic (100 Ohms differential). This is very
important to avoid any reflections, thus outputting the best Eye Diagram. Also minimize the trace length as much as
possible to minimize the resistance path. This is generally done by placing the ADV7511W close to the HDMI
connector.

ESD Protection

6.2.2.1
In order to provide ESD protection to the TMDS differential pairs, it is recommended that low capacitance (<.6pF)
varistors are used, such as the Panasonic EZAEG2A device. Please refer to ▶Figure 25 for connection of the varistors.
These should be placed as close to the TMDS lines as possible.

EMI Prevention

6.2.2.2
If it is necessary to reduce the EMI emissions (predominantly at higher frequencies), we recommend use of common
mode chokes placed in the TMDS lines as close to the ADV7511W as is possible. Two such options are the Murata
DLW21SN670HQ2L (67 ohm) or DLW21SN900SHQ2 (90 ohm).

Display Data Channel (DDC) pins

6.2.3
The Display Data Channel (DDCSCL and DDCSDA) pins need to have the minimum amount of capacitance loading
to ensure the best signal integrity. The DDCSCL and DDCSDA capacitance loading must be less than 50pF to meet the
HDMI compliance specification. The DDCSCL and DDCSDA must be connected to the HDMI connector and a pull-
up resistor to 5V is required. The pull-up resistor must have a value between 1.5KΩ and 2KΩ. The Enhanced Display
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