Table 6 Ycbcr 4:2:2 Formats (24, 20, Or 16 Bits) Input Data Mapping: 0X48[4:3]='00' (Evenly Distributed) Input Id=1 Or 2 - Analog Devices ADV7511W Hardware User's Manual

ADV7511W
YCbCr 4:2:2 Formats (24, 20, or 16 bits) Input Data Mapping:
Table 6
0x48[4:3]='00' (evenly distributed) Input ID=1 or 2
Input
Format
23 22 21
YCbCr422 Cb[11:4]
Sep. Sync
Cr[11:4]
(24 bit)
YCbCr422 Cb[9:2]
Sep. Sync
Cr[9:2]
(20 bit)
YCbCr422 Cb[7:0]
Sep. Sync
Cr[7:0]
(16 bit)
24 bit Cb[11:0]
Cr[11:0]
20 bit Cb[9:0]
Cr[9:0]
16 bit Cb[7:0]
Cr[7:0]
24 bit Y[11:0]
Y[11:0]
20 bit Y[9:0]
Y[9:0]
16 bit Y[7:0]
Y[7:0]
Input ID = 1: An input with YCbCr 4:2:2 with separate syncs can be selected by setting the Input ID (R0x15[3:0]) to 0x1. The
data bit width (24, 20, or 16 bits) must be set with R0x16 [5:4]. The three input pin assignment styles are shown in the table. The
Input Style can be set in R0x16[3:2].
Input ID = 2: An input with YCbCr 4:2:2 with embedded syncs (SAV and EAV) can be selected by setting the Input ID
(R0x15[3:0]) to 0x2. The data bit width (24 = 12 bits, 20 = 10 bits, or 16 = 8 bits) must be set with R0x16 [5:4]. The three input pin
assignment styles are shown in the table. The Input Style can be set in R0x16[3:2]. The only difference between Input ID 1 and
Input ID 2 is that the syncs on ID 2 are embedded in the data much like an ITU 656 style bus running at 1X clock and double
width.
Page 22
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20 19 18 17 16 15
Y[11:4]
Y[11:4]
Y[9:2]
Y[9:2]
Y[7:0]
Y[7:0]
Y[7:0]
Y[7:0]
Cb[7:0]
Cr[7:0]
Data<23:0>
14 13 12 11 10 9
Style 1
Style 2
Y[11:0]
Y[11:0]
Y[9:0]
Y[9:0]
Style 3
Cb[11:0]
Cr[11:0]
Cb[9:0]
Cr[9:0]
HARDWARE USER'S GUIDE
8 7 6 5 4 3
Cb[3:0] Y[3:0]
Cr[3:0] Y[3:0]
Cb[1:0] Y[1:0]
Cr[1:0] Y[1:0]
Rev.A
2 1 0
Rev A