Section 6: Functional Description; Input Connections; Unused Inputs; Video Data Capture Block - Analog Devices ADV7511W Hardware User's Manual

ADV7511W

SECTION 6: FUNCTIONAL DESCRIPTION

Input Connections

6.1

Unused Inputs

6.1.1
Any input data signals which are not used should be connected to ground.

Video Data Capture Block

6.1.2
The ADV7511W can accept video data from as few as eight pins (either YCbCr 4:2:2 double data rate [DDR] or YCbCr
4:2:2 with 2x pixel clock) to as many as 24 pins (RGB 4:4:4 or YCbCr 4:4:4). In addition it can accept HSYNC, VSYNC
and DE (Data Enable). The ADV7511W can detect all of the 59 video formats defined in the EIA/CEA-861E
specification. Either separate HSYNC, VSYNC, and DE, or embedded syncs in the style of the ITU BT.656, SMPTE
274M, and SMPTE 296M specifications are accepted. The alignment of the data can be defined as left or right justified
or as evenly distribution. In the case of even distribution, the channel data is left-justified in their respective 8-bit
fields. For timing details for video capture, see Figure 2. For complete details on how to set these, refer to the
ADV7511W Programming Guide.
The ADV7511W can accept HSYNC, VSYNC and DE (Data Enable) signals separately or as an embedded data (ITU
656 based) on the data inputs. If using separate syncs and DE is not available, the DE signal can be generated internally
in the ADV7511W.
The tables in section 6.1.2.1 define how the many different formats are accepted on the input data lines.

Video Input Connections

6.1.2.1
The following table is a summary of the input options which are shown in detail in Table 5 through Table 10.
Input ID Selection
Table 4
Input Bits per Pin Assignment Table
ID Color
0 8 ▶Table 5
1 8, 10, 12 ▶Table 6
2 8, 10, 12
3 8, 10, 12 ▶Table 7
4 8, 10, 12
6 8 ▶Table 8
6 8 ▶0
6 8, 10, 12 ▶Table 10
7 8, 10, 12 ▶Table 7
8 8, 10, 12
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Maximum Format Name
Input Clock
165.0 MHz RGB 4:4:4, YCbCr 4:4:4
165.0 MHz YCbCr 4:2:2 (even dist.)
165.0 MHz YCbCr 4:2:2 (even dist.)
82.5 MHz YCbCr 4:2:2 2X clock (even
dist.)
82.5 MHz YCbCr 4:2:2 2X clock (even
dist.)
82.5 MHz YCbCr 4:2:2 DDR (right just.)
82.5 MHz YCbCr 4:2:2 DDR (left just.)
82.5 MHz YCbCr 4:2:2 DDR (even dist.)
82.5 MHz YCbCr 4:2:2 DDR (even dist.)
82.5 MHz YCbCr 4:2:2 DDR (even dist.)
HARDWARE USER'S GUIDE
Sync Type
Separate syncs
Separate syncs
Embedded syncs
Separate syncs
Embedded syncs
Separate syncs
Separate syncs
Separate syncs
Separate syncs
Embedded syncs
Rev.A
Rev A