Mitsubishi MELSEC Q Series Programming Manual page 905

(8) Program example when the multiple CPU high-speed transmission dedicated instructions
are executed to CPU modules by turns
When the multiple CPU high-speed transmission dedicated instructions are executed to
Universal model QCPUs by turns, release an interlock to prevent the concurrent execution.
Use the cyclic transmission area device (from U3En\G10000) as an interlock.
The following shows a program example when the multiple CPU high-speed transmission
dedicated instructions are executed at CPU No.s 1 and 2 by turns.
Program example when the multiple CPU high-speed transmission dedicated instruction is
executed at CPU No.1
SM402
Turn-on for one scan
after RUN
X0
Write command
M0 U3E1\G10000.0
During execution CPU No.2 is Number of used
of the DDWR during execution blocks information
instruction of the instruction (CPU No.2)
M1
Completion device
U3E0\G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction.
SM797
DP.DDWR
U3E0\G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction.
MOV K7
SET
SET
MOV
H3E1 D0 ZR100 ZR100
Completion
status
RST
SET
7
10
7
7
SD797
Maximum number
of used blocks
(CPU No.2)
7
M0
During execution of the
DDWR instruction
7
U3E0\
G10000.0
7
CPU No.1 is during
execution of the
instruction
7
K100 D1
Number of
write points
M1
Completion
device
M0
During execution of
the DDWR instruction
U3E0\
G10000.0
CPU No.1 is during of
the instruction
10-9