Mitsubishi MELSEC Q Series Programming Manual page 912

D(P).DDWR
In any of the following cases, the instruction is completed abnormally, and an error code is
stored into a device specified at completion status storage device ( +0).
(1) The request of the instruction to the target CPU is more than the acceptable value (no empty
blocks exist in the multiple CPU high speed transmission area).
(2) A device for another CPU specified at
range.
(3) The number of write points set with the D(P).DDWR instruction is 0.
(4) The response of the instruction from another CPU cannot be returned (no empty blocks exist
in the multiple CPU high speed transmission area).
Program Example
(1) This program stores data by 10 words starting from D0 in host CPU into W10 or later in CPU
No.2 when X0 turns on.
[Ladder mode]
[Ladder mode]
Caution
(1) Digit specification of bit device is possible for n,
specification of bit device is made to
• Digits are specified by 16 bits (4 digits).
• The start bit device is multiples of 16 (10
(2) Execute this instruction after checking that the write target CPU is powered on. Not doing so
may end up no processing.
(3) If changing a range of the device specified at setting data between after execution of the
instruction and turn-on of the completion device, data to be stored by system (completion
status, completion device) cannot be stored normally.
(4) SB, SW, SM, and SD include system information area. Take care not to destroy the system
information when writing data to the devices above with the D(P).DDWR instruction of the
multiple CPU high-speed transmission dedicated instruction.
10-16
cannot be used at another CPU, or is out of device
S1
, and . Note that when the digit
S2 D1
or , the following conditions must be met.
S2 D1
).
H
S1
(Error code: 0010 )
H
(Error code: 1001 )
H
(Error code: 1080 )
H
(Error code: 1003 )
H