Mitsubishi MELSEC Q Series Programming Manual page 915

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
(1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated
instruction cannot be used in the setting
• The reserved CPU has been specified.
• Unmounted CPU has been specified.
• The result of dividing the start I/O number of another CPU by 16n is outside the range of
3E0 to 3E3
H
• The instruction was executed without setting "Use multiple CPU high speed
transmission".
• The instruction was executed with the Q02UCPU.
• Host CPU has been specified.
• The CPU where the instruction cannot be executed has been specified.
(2) The instruction cannot be executed with the CPU.
• Another CPU does not support this instruction.
(3) The number of devices is wrong.
(4) The device that cannot be used for the instruction has been specified.
(5) A device has been specified by the character string that cannot be used.(Error code: 4354)
(6) The number of read points (
In any of the following cases, the instruction is completed abnormally, and an error code is
stored into a device specified at completion status storage device (
(1) The request of the instruction to the target CPU is more than the acceptable value (no empty
blocks exist in the multiple CPU high speed transmission area).
(2) A device for another CPU specified at
range.
(3) The number of read points set with the D(P).DDRD instruction is 0.
(4) The response of the instruction from another CPU cannot be returned (no empty blocks exist
in the multiple CPU high speed transmission area).
H.
+1)is other than 0 to 100.
S1
S2
cannot be used at another CPU, or is out of device
D(P).DDRD
(Error code: 4350).
(Error code: 4351)
(Error code: 4352)
(Error code: 4353)
(Error code: 4355)
+0).
S1
(Error code: 0010 )
H
(Error code: 1001H)
(Error code: 1081 )
H
(Error code: 1003 )
H
10-19
7
10
7
7
7
7
7
7