Vtr Codec Block Diagram - Panasonic AJ-SDX900P Service Manual

VTR CODEC BLOCK DIAGRAM

IC3006<3>
P3 P3001
4
19B 19B CLK_BB(27MHz)
IC3006<3>
12
P3 P3001
37A 37A PREP SAVE P
IC3031<9>
P3001
P3
58-66
8- 8-
PREP_Y [2-9]
15A 15A
P3 P3001
411FIL
68-75
8- 8-
PREP_C [2-9]
15B 15B
IC3006<3>
P3001
P3
1
18A 18A FRM_BB (27M_FRP)
P3 P3001
27A 27A
REC_PCM12
28A 28A REC_PCM34
TP3009
CLK27
IC3009<3>
6 6 14
FS256
11
PREP_SAVE_P
IC3024<5> A15
27MHz H16
IC3010<3> 7
x 2
PLL
12,13
54MHz
11-19 Y_REC OUT [0-7]
D15-E12
1-9 C_REC OUT [0-7]
F16-G13
21,41
CLK135
13.5MHz J12
PREP50
FRP
H15 (FPGA)
54MHz
H1
IC3023<5>
TP3014
FRM
38
54MHz
SDRAM
3
REC_PCM12
REC_PCM34
IC3011<3>
7
x 8
8
PLL
IC3012<3>
12
COMP_CLK
1 4
IC3013<3>
J14 J15 J13 J1
1 4
K15
36MHz
x 27/3 x 1/2
TP3008
CK18
IC3005<3> IC3007<3>
12 11 1 4 1
K13
1/2
IC3005<3> IC3008<3>
9 8
FRP
COMP_A[0-7]
T2-P5
M1-P1 COMP_B[0-7]
K4 PREPRO_FRP18
IC3026<6>
24 18
AUDIO
Delay
25 17
IC3027<6>
16,18,26
FS256
79-82
83-86
22
36MHz
TP3011
BCK
IC3015<4>
41,45
BCK_INT
TP3012
MCK
IC3016<4>
40,44
COMP100 MCK_INT
4 24
18MHz
COMP_CLK18
TP3013
LRCK
121-114
IC3019<4>
39,55
LRCK_INT
138-130
141,142
FRP
IC3020<4>
PB_PCM
13
REC_PCM12
56
REC_PCM34
P3001 P3
51- 51-
CMP_BUS_A [0-3]
54A 54A
P3001 P3
55- 55-
CMP_BUS_B [0-3]
58A 58A
P3001 P3
BCK_SDI 41A 41A
BCK_FPGA 27B 27B
BCK
45B 45B
BCK_68P
47A 47A
P3001 P3
MCK_SDI 41B 41B
MCK_FPGA 26B 26B
MCK 44B 44B
MCK_68P 47B 47B
P3001 P3
LRCK_SDI 40B 40B
LRCK_FPGA
26A 26A
LRCK 44A 44A
LRCK_68P 48B 48B
P3001 P3
PBPCM12_SDI 42A 42A
PBPCM34_SDI
43A 43A
PB_PCM12 29A 29A
PB_PCM34 30A 30A
P3001 P3
CLK18M 31B 31B