System Block Diagram (Overall) - Panasonic AJ-SDX900P Service Manual

SYSTEM BLOCK DIAGRAM (OVERALL)

REAR AUDIO
DC IN UNREG
BRAKER
TRIAX
BATTERY IN
DC OUT
26PIN OUT
REAR MIC IN (OPTION)
(CH1-2)
PRE
AUDIO IN
100PIN AMP
AUDIO IN
AUDIO OUT
AUDIO OUT
ECU ECU
VIDEO OUT VIDEO_OUT
EVF
LENS
CCD SENSOR PRE AMP
B
G
+
BLACK
LPF
SAMPLE
- SHADING
TEMP GATE
SENSOR
DELAY
DAC(8bit-12ch )
BLEMISH
R (EEPROM)
ROM
DRIVE
V-CCD
DAC(8bit-12ch )
DA DATA
PULSE
(EEPROM)
DRIVER
PULSE
DAC(8bit-2ch)
(EEPROM)
PULS_PLD
CCD DRIVE PULSE GENERATOR (FPGA)
H LOCK TEST SIGNAL
DAC(8bit)
36MHz PLL
FRONT SW
RET_SW
MENU SW
START SW
JOG
SHUTTER
ABB/AWB
CC/ND FILTER
WHITE BAL(A/B/PRE)
SIDE SW
OUTPUT(KNEE/BARS)
GAIN(L/M/H)
SYNCRO SCAN(+/-)
P/S
S-GAIN
+ -
USER SW(1/2)
MARKER SW
VTR(STBY/SAVE)
MODE CHECK
FRONT PRE AMP
(CH1/2)
PRE
FRONT MIC IN AMP
LOWCUT
AMP
(CH3/4)
LOWCUT
REC CH
AUDIO IN AMP
SELECT
WIRELESS
WIRELESS AMP
68PIN
AMP
AUDIO OUT
26PIN_AUDIO OUT SELECT
AMP
(OPTION)
(CH1/2)
AUDIO OUT AMP
HEAD PHONE
AMP
(FRONT/REAR)
MONITOR DOLBY
SELECT
SPEAKER AMP
INTERFACE
RET
L_SIDE
GENLOCK/
68PIN GEN LOCK/
VIDEO_IN
AUDIO IN VIDEO IN
TC IN TC IN
68PIN
VIDEO OUT
TC OUT TC OUT
68PIN
AUDIO OUT
CAM_OUT
CAM OUT
26PIN_OUT
(OPTION)
26PIN_AUDIO OUT
(OPTION)
RCU
RET_SW
SDRAM SDRAM
X2
PRE PROCESS
PLL
SDRAM
STAR_MINE
36MHz
(DSP)
GAIN
BLEMISH
PED
FM_FPGA
GAIN CNTL PRE ADCX3
COMP
CNTL
CNTL (AWB/ KNEE (12bits)
(ABB) GAMMA/KNEE
MEMORY
W-SHD)
DETAIL
AD_CLK CONTROL
MATRIX
(VFR)
BLOCK DATA
FLARE
CB GEN
DIGITAL
SHADING
SHD DATA
DAC(8bit-12ch )
SHD
(EEPROM)
SRAM
DAC(12bit-4ch)
X3
VIDEO IN
27MHz PLL
HD/VD(VFR)
DIGITAL
36MHz PLL
SERIAL CONTROL
DECODER
GEN LOCK IN
SYNC H LOCK
SEP 27MHz PLL
SC LOCK
SC SEP
4Fsc PLL
VIDEO IN
GENLOCK/
VIDEO_IN
NVRAM
RET
ECU
RCU
MIC FRONT CH1 VR AGC
ADC
VR CH2 VR LMT
MIC AGC
ADC
LMT
LCD
NV RAM LCD uCOM
DRIVER
RTC
DAC
DAC
CAM_OUT
SDI-TX
100PIN_OUT
(OPTION)
26PIN_OUT
(OPTION)
SD SDI
P/S
ENCORDER
MECHANICAL
RELAY
CAM_DSP
DAC DACX3 DAC DAC
X8
(10bits) (10bits) (12bits) (12bits)
PLL
( Y/Pr/Pb )
PREP50
411FIL
36MHz 27MHz
(FPGA)
IF_LSI
DOWN-
X2
CONV
SDRAM
PLL
CHAR_FPGA(FPGA)
OUTPUT SEL
CHAR_ADD
SERIAL
METADATA ADD
CAMERA ID
CONTROL
ADD
SYNC GEN
FIFO
FONT_ROM
FLASH
FLASH_MEM
(CHAR FONT)
SRAM
CAM_MICON
FLASH
CAM SYS CPU
AUDIO_LCD
NDF SLAVE HOLD iREC
-0-
CTL VITCG VIUBG TIME
-
10-
-
h min s frm
20-
-
TAPE
30-
E F
-
BATT
40-
1 2
RF SERVO HUMID SLACK -db
3 4
CYLINDER MOTOR
PL2 PR2
FER2
FEL2
RR2
RL2
VIDEO_OUT
PR1 PL1
CODEC ECC_SYS
AUDIO RECCLK
PLL Xtal
PRE REC
(FPGA)
COMP100
PRE REC MEMORY
(OPTION)
ECC200
SDRAM SDRAM SDRAM SDRAM
PRE_REC
SDRAM SDRAM SDRAM SDRAM
INTERVAL REC
META DATA
AUDIO CH SEL
AUDIO(CH1/2/3/4)
AUDIO LEVEL DET
METADATA/CHAR DATA/
AUDIO 1KHz GEN
uCOM COMUTICATION
HID GEN
EVR
SYS IF
VTR SYS CPU
TC IN
TC OUT
SERIAL
SD CARD
CARD
uCOM
RS-232C
(9pin)
HEAD WIDTH
RL1
RR1
RP 18um
FEL1 PB 24um
FER1
FE 21um
H_BUFF
RFEQ
BUFF REC
RECCUR ADJ AMP
RPL1
HEAD
LPF
AMP RPL2
RFLP
AMP LPF
(LEVEL ADJ)
REC
BUFF
RECCUR ADJ
AMP
RPR1
HEAD
LPF
RPR2
AMP
RFLP
AMP
LPF
(LEVEL ADJ)
PBL1
HEAD
ENVADJ ENVDET PBL2
AMP
HEAD PBR1
ENVADJ ENVDET
AMP
PBR2
FE35OSC FE1
RECCUR ADJ
FE35OSC FE2
ENVADJ
FE35OSC
FE3
FE35OSC
FE4
SERVO
MOTER
DRIVE
FG
SERIAL
PG & FG
REGEN
AMP
(PLD)
SOLENOIDE
DRIVE
SERVO SENSOR
uCOM
DRIVE &
AMP
CTL
CTL
AMP
EE-
PROM
VTR_POWER
CUE
R/P
PB AMP
CUE R/P HEAD
HSW
REC AMP
CUE
BIAS OSC
CUE ERASE HEAD
CUE/CTL
ERASE
CTL ERASE HEAD