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Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual

Image data transmit & receive port 2 bit serial with clock and sync pcie 4 lane module lvds
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DYNAMIC ENGINEERING
150 DuBois St. Suite C, Santa Cruz, CA 95060
831-457-8891
Fax 831-457-4793
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PCIeBiSerialDb37-BA22
Image Data Transmit & Receive Port
2 bit serial with clock and sync
PCIe 4 lane Module
LVDS
Revision C
Corresponding Hardware: Revision 1
10-2009-0402
FLASH 0303
Embedded Solutions
Page 1

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Summary of Contents for Dynamic Engineering PCIeBiSerialDb37-BA22

  • Page 1 DYNAMIC ENGINEERING 150 DuBois St. Suite C, Santa Cruz, CA 95060 831-457-8891 Fax 831-457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PCIeBiSerialDb37-BA22 Image Data Transmit & Receive Port 2 bit serial with clock and sync PCIe 4 lane Module LVDS Revision C...
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right to make improvements or changes in the product described in this document at any time and without notice.

  • Page 3: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION 6   ADDRESS MAP 14     Base Address Map   Channel Address Map   Programming   Base Register Definitions   BA22_BASE_BASE   BA22_BASE_ID   BA22_BASE_STATUS   BA22_BASE_PLL_WRITE BA22_BASE_PLL_READ   Channel Bit Maps   BA22_CHAN_CNTRL  ...
  • Page 4 APPLICATIONS GUIDE 40     Interfacing   Construction and Reliability   Thermal Considerations   Warranty and Repair   Service Policy   Out of Warranty Repairs SPECIFICATIONS 43   ORDER INFORMATION 44   Embedded Solutions Page 4...
  • Page 5 List of Figures   FIGURE 1 PCIEBISERIALDB37BA22 BLOCK DIAGRAM   FIGURE 2 PCIEBISERIALDB37BA22 TIMING DIAGRAM   FIGURE 3 PCIEBISERIALDB37BA22 IMAGE DIAGRAM   FIGURE 4 PCIEBISERIALDB37BA22 INTERNAL ADDRESS MAP BASE FUNCTIONS   FIGURE 5 PCIEBISERIALDB37BA22 CHANNEL ADDRESS MAP   FIGURE 6 PCIEBISERIALDB37BA22 CONTROL BASE REGISTER BIT MAP  ...

  • Page 6: Product Description

    Engineering is happy to assist in your decision regarding architecture and other trade- offs with the form factor decision. Dynamic Engineering has carriers for IP and PMC modules for most systems, and is adding more as new solutions are requested by our clients.
  • Page 7 board. “BA22” is set to use the LVDS standard, and supports one Transmit and one Receive channel. The transmitter and receiver are designed to interface with a 2 bit serial data stream with reference sync and clk. The base frequency is 73.636 MHz. The transmit frequency is programmable using the A output from the PLL.

  • Page 8: Figure 1 Pciebiserialdb37Ba22 Block Diagram

    BA22 (2 x 4 x LVDS) termination TX State RX State Machine Machine TX FIFO RX FIFO ~262K x 32 5K x 32 Data Flow Control PCI IF Bridge PCIe x4 Figure 1 PcieBiSerialDb37BA22 Block Diagram BA22 supports transmission and reception of serialized 2 bit wide data. The Data transfer is controlled with a continuous clock plus sync pattern.
  • Page 9 Custom cables can be manufactured to your requirements. The loop-back IO definitions are toward the end of this manual. Please contact Dynamic Engineering with your specifications. In the “BA22” design the Termination and Direction controls are set in the VHDL for the IO.
  • Page 10 Windows® , Linux and other OS can be used to interface with this design. For Dynamic Engineering drivers please check the DDS [Dynamic Data Sheet on-line] . Custom drivers can be written for your situation. Existing drivers are “free” to BA22 clients.

  • Page 11: Figure 2 Pciebiserialdb37Ba22 Timing Diagram

    If you see what you need in one version and prefer it on another please contact Dynamic Engineering about porting the design. In most cases it will require a recompile of the VHDL and not much more. We do a lot of “just like but different “...

  • Page 12: Figure 3 Pciebiserialdb37Ba22 Image Diagram

    changing on the rising edge, and stable on the falling edge. The transmit rate is programmable for the BA22. PLL channel A is programmed to 73.636 MHz for a 73.636 MHz. output rate. Sync programmable both for pattern and number of pixels. In addition a PreAmble is provided again with programmable pattern and number of pixels.
  • Page 13 lines per frame [Frame Length], and the repetition rate. The Blanking time is the difference in the frame repetition rate and the size of the image and idle time. It is programmed in terms of the reference rate clock. The time does not have to be an integer number of pixels.

  • Page 14: Address Map

    Address Map Base Address Map Function Offset // PCIeBiSerialDb37BA22 BASE definitions #define BA22_BASE_BASE 0x0000 // 0 BA22Base Base control register #define BA22_BASE_USER_SWITCH 0x0004 // 1 BA22Base User DIP switch read #define BA22_BASE_XILINX_REV 0x0004 // 1 BA22Base Xilinx revision read port #define BA22_BASE_XILINX_DES 0x0004 // 1 BA22Base Xilinx design read port #define BA22_BASE_STATUS...

  • Page 15: Channel Address Map

    Channel Address Map Function Offset from Channel Base Address #define CHAN_CNTRL 0x00000000 // 0 General control register #define CHAN_STATUS 0x00000004 // 1 Interrupt status port #define CHAN_INT_CLEAR 0x00000004 // 1 Interrupt clear port #define CHAN_WR_DMA_PNTR 0x00000008 // 2 Write DMA dpr physical PCI address register #define CHAN_TX_FIFO_COUNT 0x00000008 // 2 Tx FIFO count read port #define CHAN_RD_DMA_PNTR 0x0000000C // 3 Read DMA dpr physical PCI address register...

  • Page 16: Programming

    The Driver comes with reference software showing how to use the card and reference frequency files to allow the user to duplicate the test set-up used in manufacturing at Dynamic Engineering. Using simple, known to work routines is a good way to get acquainted with new hardware.
  • Page 17 Packet loaded if shorter than the FIFO size. For reception it means that the FIFO is under HW control and the delay from starting reception to starting DMA won’t cause an overflow condition. DMA can be programmed with a specific length. The length can be as long as you want within standard memory limitations.

  • Page 18: Base Register Definitions

    Base Register Definitions BA22_BASE_BASE [$00 Base Control Register Port read/write] DATA BIT DESCRIPTION 31-2 spare ClrPll PllProgEn Figure 6 PcieBiSerialDb37BA22 Control Base Register Bit Map This is the base control register for the BA22. The features common to all channels are controlled from this port.

  • Page 19: Ba22_Base_Id

    BA22_BASE_ID [$04 Switch and Design number port read only] DATA BIT DESCRIPTION 31-24 spare 23-8 Design ID and Revision DIP switch Figure 7 PcieBiSerialDb37BA22 ID and Switch Bit Map The DIP Switch is labeled for bit number, and ‘1’ ‘0’ in the silk screen. The DIP Switch can be read from this port and used to determine which PcieBiserialDb37BA22 physical card matches each PCI address assigned in a system with multiple cards installed.

  • Page 20: Ba22_Base_Status

    BA22_BASE_STATUS [$08 Board level Status Port read only] DATA BIT DESCRIPTION 31-19 set to ‘0 18-16 PllPckDnCnt 15-13 set to ‘0’ PllNakLat PllPacketDoneLat PllRdFifoMt PllWrFifoMt Pll Idle set to ‘0’, reserved for additional channels Unmasked Ch0 Interrupt Figure 8 PcieBiSerialDb37BA22 Status Port Bit Map Channel Interrupt –...

  • Page 21: Ba22_Base_Pll_Write Ba22_Base_Pll_Read

    BA22_BASE_PLL_WRITE BA22_BASE_PLL_READ [$10 Board level PLL FIFO Port] DATA BIT DESCRIPTION 31-0 LW written to / read from PLL Figure 9 PcieBiSerialDb37BA22 PLL FIFO Port Bit Map The transmit FIFO is monitored by the PLL state-machine. When the FIFO is written to the first word is read by the state-machine and parsed.

  • Page 22: Channel Bit Maps

    Channel Bit Maps The BA22 design has 1 channel. The basic control signals are the same for the channel base, channel status, FIFO and DMA interfaces across multiple designs. Notes: The offsets shown are relative to the channel base address not the card base address. BA22_CHAN_CNTRL [0x0] Channel Control Register (read/write) Channel Control Register...
  • Page 23 FIFO Transmitter/Receiver Reset: When set to a one, the transmit and/or receive FIFOs will be reset. When these bits are zero, normal FIFO operation is enabled. In addition the Transmit and Receive State Machines are also reset. Write/Read DMA Interrupt Enable: These two bits, when set to one, enable the interrupts for DMA writes and reads respectively.
  • Page 24 TxFifoAmtInt when set enables the programmable interrupt based on the Transmit FIFO level. Set the level to provide enough time to load more data. Since a programmed level the amount of room [minimum] is already known. Alternatively use DMA for automatic data transfer.

  • Page 25: Ba22_Chan_Status

    BA22_CHAN_STATUS [0x4] Channel Status Read/Clear Latch Write Port Channel Status Register Data Bit Description Interrupt Status LocalInt Transmitter Idle 28-27 spare Tx DMA FIFO AFL Tx DMA FIFO AMT spare BurstInIdle BurstOutIdle Ext FIFO 1 FULL Ext FIFO 0 FULL spare RxFifoOvFlLat TxFifoUnFlLat...
  • Page 26 status is active high. The Full and Empty status come from the “DMA” FIFO’s while the Almost Full and Almost Empty status reflects the state of the total FIFO. 0x13 would correspond to empty Rx and empty Tx DMA FIFO’s. The DMA FIFO’s are the pair of internal FIFO’s which interact with the DMA engine.
  • Page 27 Write/Read DMA Error Occurred: When a one is read, a write or read DMA error has been detected. This will occur if there is a target or master abort or if the direction bit in the next pointer of one of the chaining descriptors is incorrect. A zero indicates that no write or read DMA error has occurred.
  • Page 28 programmed count. The software can do a looped write or use DMA to load the programmed count amount of data to the storage FIFO. The signal is latched and can be cleared via write back with this bit set. The signal can be used to generate an interrupt if desired.

  • Page 29: Ba22_Chan_Wr_Dma_Pntr

    BA22_CHAN_WR_DMA_PNTR [0x8] Write DMA Pointer (write only) BurstIn DMA Pointer Address Register Data Bit Description 31-2 First Chaining Descriptor Physical Address direction [0] end of chain Figure 12 PcieBiSerialDb37BA22 Write DMA pointer register This write-only port is used to initiate a scatter-gather write [TX] DMA. When the address of the first chaining descriptor is written to this port, the DMA engine reads three successive long words beginning at that address.

  • Page 30: Ba22_Chan_Tx_Fifo_Count

    BA22_CHAN_TX_FIFO_COUNT [0x8] TX [Target] FIFO data count (read only) TX FIFO Data Count Port Data Bit Description 31-0 TX Data Words Stored Figure 13 PcieBiSerialDb37BA22 TX FIFO data count Port This read-only register port reports the number of 32-bit data words in the Transmit FIFO.

  • Page 31: Ba22_Chan_Rx_Fifo_Count

    Notes: 1. Writing a zero to this port will abort a write DMA in progress. 2. End of chain should not be set for the address written to the DMA Pointer Address Register. End of chain should be set when the descriptor follows the last length parameter.

  • Page 32: Ba22_Chan_Tx_Amt_Lvl

    BA22_CHAN_TX_AMT_LVL [0x14] Tx almost-empty level (read/write) Tx Almost-Full Level Register Data Bit Description 31-0 Tx FIFO Almost-Empty Level Figure 17 PcieBiSerialDb37BA22 TX ALMOST EMPTY LEVEL register This read/write port accesses the almost-empty level register. When the number of data words in the transmit data FIFO is less than this value, the almost-empty status bit will be set.

  • Page 33: Ba22_Chan_Ready_Cnt

    BA22_CHAN_READY_CNT [0x24] Tx Ready Count(read/write) Tx Ready Count Register Data Bit Description 31-0 Amount of data required to start transmission Figure 19 PcieBiSerialDb37BA22 TX Ready Count Register This read/write port accesses the Ready Count register. When the number of data words in the transmit data FIFO is greater or equal to this value, the FIFO READY signal to the TX State Machine will be set.

  • Page 34: Ba22_Chan_Line_Length

    BA22_CHAN_LINE_LENGTH [0x2C] Tx Line Length(read/write) Tx Line Length Register Data Bit Description 31-0 Amount of data required to start transmission Figure 21 PcieBiSerialDb37BA22 TX Line Length Register This read/write port accesses the Line Length register. Set the number of pixels per line to be transmitted with this register.

  • Page 35: Ba22_Chan_Frame_Length

    BA22_CHAN_FRAME_LENGTH [0x34] Tx Frame Length(read/write) Tx Frame Length Register Data Bit Description 31-0 Amount of data required to start transmission Figure 23 PcieBiSerialDb37BA22 TX Frame Length Register This read/write port accesses the Frame Length register. Set the number of Lines per Frame to be transmitted with this register.

  • Page 36: Chan_Tx_Syncpat

    transmitted. Data is held as “00” during transmission. CHAN_TX_SyncPat [0x40] Tx Sync (read/write) Tx Sync Pattern Register Data Bit Description Control Pattern to send during Sync Figure 26 PcieBiSerialDb37BA22 TX Sync Pattern Register This read/write port accesses the Sync Pattern register. Set the control data to send during Sync time.

  • Page 37: Chan_Tx_Datapat

    during Idle time. Idle will be sent for the programmed length between lines [Idle Time] and between frames as programmed with the difference in frame time and the master sync period. CHAN_TX_DataPat [0x4C] Tx Data Pattern (read/write) Tx Data Pattern Register Data Bit Description Control Pattern to send during Data...

  • Page 38: Loop-Back

    Loop-back The Engineering kit includes reference software, utilizing external loop-back tests. The test set-up included PcieBiSerialDb37BA22 and loop-back plug. The Pin numbers are for the interconnections on the Loop-back plug. The IO names can be used to accommodate a different set-up. The loop-back plug is a DB37 connector with the interconnections protected with a connector shell.

  • Page 39: Pcie Module Front Panel Io Interface Pin Assignment

    PCIe Module Front Panel IO Interface Pin Assignment The figure below gives the pin assignments for the IO Interface on the PcieBiSerialDb37BA22. IO_0p (TxPSync+) IO_0m (TxSync-) IO_1p (TxPDataU+) IO_1m (TxDataU-) IO_2p (TxPDataL+) IO_2m (TxDataL-) IO_3p (TxPClk+) IO_3m (TxClk-) IO_4p (RxPSync+) IO_4m (RxPSync-) IO_5p (RxPDataU+) IO_5m (RxPDataU-)

  • Page 40: Applications Guide

    Applications Guide Interfacing The pin-out tables are displayed with the pins in the same relative order as the actual connectors. Some general interfacing guidelines are presented below. Do not hesitate to contact the factory if you need more assistance. Watch the system grounds. All electrically connected equipment should have a fail-safe common ground that is large enough to handle all current loads without affecting noise immunity.

  • Page 41: Construction And Reliability

    Construction and Reliability PCIe Modules were conceived and engineered for rugged industrial environments. The PcieBiSerialDb37BA22 is constructed out of 0.062 inch thick high temperature ROHS compliant material. The traces are matched length from the FPGA ball to the IO pin. The analog switches and termination resistors are located directly under the transceivers and connected with “zero stub”...

  • Page 42: Warranty And Repair

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.

  • Page 43: Specifications

    Specifications Logic Interface: PCIe 1-4 lanes. 4 lanes recommended Digital Parallel IO: LVDS IO Digital Serial IO: 2 bit serial with sync and reference clock.. Data valid on falling edge of clock. 76.636 MHz for initial target design. DIP Switch: DipSwitch supplied for board identification and other user purposes.
  • Page 44 DB37 cable compatible with PCIeBiSerialDB37. Twisted pairs on correct pin pairs. http://www.dyneng.com/DBcabl37.html PCIe BiSerial DB37 BA22 Eng Kit : Windows Driver software, Loop-Back Plug, reference schematics. Recommended for first time purchases. http://www.dyneng.com/pciebiserialdb37.html All information provided is Copyright Dynamic Engineering Embedded Solutions Page 44...

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