Chan_Tx_Datapat; Figure 29 Pciebiserialdb37Ba22 Tx Data Pattern Register - Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual

during Idle time. Idle will be sent for the programmed length between lines [Idle Time]
and between frames as programmed with the difference in frame time and the master
sync period.

CHAN_TX_DataPat

[0x4C] Tx Data Pattern (read/write)
Tx Data Pattern Register
Data Bit Description
7-0 Control Pattern to send during Data

Figure 29 PcieBiSerialDb37BA22 TX Data Pattern Register

This read/write port accesses the Data Pattern register. Set the control data to send
during Data transmission time. The Data control word will be sent on the control line in
parallel with the transmitted data.
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