Chan_Tx_Syncpat; Chan_Tx_Synclen; Chan_Tx_Idlepat; Figure 26 Pciebiserialdb37Ba22 Tx Sync Pattern Register - Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual

transmitted. Data is held as "00" during transmission.

CHAN_TX_SyncPat

[0x40] Tx Sync (read/write)
Data Bit

Figure 26 PcieBiSerialDb37BA22 TX Sync Pattern Register

This read/write port accesses the Sync Pattern register. Set the control data to send
during Sync time. Sync will be sent when the Master Sync has been detected for
SyncLen pixels. If programmed to 0 length the Sync is skipped.

CHAN_TX_SyncLen

[0x44] Tx Sync Length(read/write)
Data Bit
15-0

Figure 27 PcieBiSerialDb37BA22 TX Sync Length Register

This read/write port accesses the Sync Length register. If programmed to 0 length the
Sync is skipped. If set to a non-zero length, that number of PreAmble pixels is
transmitted. Data is held as "00" during transmission.

CHAN_TX_IdlePat

[0x48] Tx Idle Pattern(read/write)
Data Bit

Figure 28 PcieBiSerialDb37BA22 TX Idle Pattern Register

This read/write port accesses the Idle Pattern register. Set the control data to send
Tx Sync Pattern Register
7-0
Tx Sync Length Register
Tx IDLE Pattern Register
7-0
Embedded Solutions
Description
Control Pattern to send during Sync
Description
Number of Sync pixels to send
Description
Control Pattern to send during IDLE
Page 36