Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual page 28

programmed count. The software can do a looped write or use DMA to load the
programmed count amount of data to the storage FIFO. The signal is latched and can
be cleared via write back with this bit set. The signal can be used to generate an
interrupt if desired.
RxAFLvlIntLat: When set the Rx Data FIFO has become almost Full based on the
programmed count. The software can do a looped read or use DMA to unload the
programmed count amount of data to the system memory. The signal is latched and
can be cleared via write back with this bit set. The signal can be used to generate an
interrupt if desired.
TX FRAME DONE LAT: is set at the end of each frame completed. The bit is latched
and cleared by writing back to this bit position. If enabled this status can cause an
interrupt. The status and interrupt can be used for a heart-beat, trigger another DMA
transfer etc.
Embedded Solutions Page 28