1. Manuals
  2. Brands
  3. Dynamic Engineering Manuals
  4. Control Unit
  5. PMC-BISERIAL-III RL1
  6. User manual

Dynamic Engineering PMC-BISERIAL-III RL1 User Manual

Eight-channel uart interface pmc module
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
DYNAMIC ENGINEERING
(831) 457-8891 Fax (831) 457-4793
PMC-BISERIAL-III RL1
Eight-Channel UART Interface
Corresponding Hardware: Revision D
Corresponding Firmware: Revision A
150 DuBois, Suite C
Santa Cruz, CA 95060
http://www.dyneng.com
sales@dyneng.com
Est. 1988
User Manual
PMC Module
Revision A
10-2005-0204

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the PMC-BISERIAL-III RL1 and is the answer not in the manual?

Questions and answers

Related Manuals for Dynamic Engineering PMC-BISERIAL-III RL1

Summary of Contents for Dynamic Engineering PMC-BISERIAL-III RL1

  • Page 1 DYNAMIC ENGINEERING 150 DuBois, Suite C Santa Cruz, CA 95060 (831) 457-8891 Fax (831) 457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual PMC-BISERIAL-III RL1 Eight-Channel UART Interface PMC Module Revision A Corresponding Hardware: Revision D 10-2005-0204 Corresponding Firmware: Revision A...
  • Page 2 Dynamic Engineering has made every effort to ensure that this manual is accurate and complete. Still, the company reserves the right...

  • Page 3: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION PROGRAMMING ADDRESS MAP Register Definitions RL1_BASE_CONTROL RL1_USER_SWITCH RL1_CHAN_0-7_CONTROL RL1_CHAN_0-7_STATUS RL1_CHAN_0-7_WR_DMA_PNTR RL1_CHAN_0-7_TX_FIFO_COUNT RL1_CHAN_0-7_RD_DMA_PNTR RL1_CHAN_0-7_RX_FIFO_COUNT RL1_CHAN_0-7_FIFO RL1_CHAN_0-7_TX_AMT_LVL RL1_CHAN_0-7_RX_AFL_LVL RL1_CHAN_0-7_TX_CONTROL RL1_CHAN_0-7_RX_CONTROL RL1_CHAN_0-7_TX_START_LATCH RL1_CHAN_0-7_RX_START_LATCH RL1_CHAN_0-7_RX_BYTE_COUNT Loop-back PMC PCI PN1 INTERFACE PIN ASSIGNMENT PMC PCI PN2 INTERFACE PIN ASSIGNMENT FRONT PANEL I/O PIN ASSIGNMENT APPLICATIONS GUIDE Interfacing...
  • Page 4 THERMAL CONSIDERATIONS WARRANTY AND REPAIR Service Policy Out of Warranty Repairs For Service Contact: SPECIFICATIONS ORDER INFORMATION SCHEMATICS Embedded Solutions Page 4 of 37...
  • Page 5 FIGURE 7 PMC-BISERIAL-III RL1 CHANNEL STATUS PORT FIGURE 8 PMC-BISERIAL-III RL1 WRITE DMA POINTER REGISTER FIGURE 9 PMC-BISERIAL-III RL1 TX FIFO DATA COUNT PORT FIGURE 10 PMC-BISERIAL-III RL1 READ DMA POINTER REGISTER FIGURE 11 PMC-BISERIAL-III RL1 RX FIFO DATA COUNT PORT...

  • Page 6: Product Description

    Product Description The PMC-BiSerial-III RL1 is a part of the PMC Module family of modular I/O products by Dynamic Engineering. It meets the PMC and CMC draft Standards. In standard configuration, the PMC-BiSerial-III RL1 is a Type 1 mechanical with only low profile passive components on the back of the board, one slot wide, with 10 mm inter-board height.

  • Page 7: Figure 2 Pmc-Biserial-Iii Rl1 Block Diagram

    FIGURE 2 PMC-BISERIAL-III RL1 BLOCK DIAGRAM The PMC-BiSerial-III RL1 configuration is shown in figure 2. The protocol implemented provides eight I/O channels each consisting of RS-485 transmit and receive data. The on-board PLL is used to generate two clocks that can be independently selected by each channel in the design.
  • Page 8 If your carrier has non-standard connectors (height) to mate with the PMC-BiSerial-III RL1, please let us know. We may be able to do a special build with a different height connector to compensate.

  • Page 9: Theory Of Operation

    ‘1’ if this descriptor is the last in the chain. Bit one is set to a ‘1’ if the I/O transfer is from the PMC-BiSerial-III RL1 board to host memory, and a ‘0’ if the transfer is from memory to the board. These bits are then replaced with zeros to determine the address of the next descriptor, if there is one.
  • Page 10 FIFO with the unfilled bytes set to zeros. Also if the Receive Start Clear Enable is set, the Receiver Enable bit will be cleared. Otherwise the receiver will remain enabled and will wait for the next start-bit to continue receiving data. TX FIFO almost empty and RX FIFO almost full levels are programmable by writing values into the respective FIFO level registers.

  • Page 11: Programming

    Programming Programming the PMC-BiSerial-III RL1 requires only the ability to read and write data from the host. The base address is determined during system configuration of the PCI bus. The base address refers to the first user address for the slot in which the PMC is installed.

  • Page 12: Address Map

    Address Map Register Name Offset Description RL1_BASE_CONTROL 0x0000 Base Control Register RL1_PLL_WRITE 0x0000 Base Control - Bits 16-19 Used for PLL Control RL1_PLL_READ 0x0004 Switch Port Bit 19 Used for pll_sdat Input RL1_USER_SWITCH 0x0004 User Switch Read Port and Xilinx Design Revision RL1_CHAN_0_CONTROL 0x0010 Channel 0 Control Register...
  • Page 13 0x0164 Channel 7 RX Control Register RL1_CHAN_7_TX_START 0x0168 Channel 7 TX Start Latch RL1_CHAN_7_RX_START 0x016C Channel 7 RX Start Latch RL1_CHAN_7_RX_BYTE_COUNT 0x016C Channel 7 RX Byte Count FIGURE 3 PMC-BISERIAL-III RL1 XILINX ADDRESS MAP Embedded Solutions Page 13 of 37...

  • Page 14: Register Definitions

    15-0 Spare FIGURE 4 PMC-BISERIAL-III RL1 BASE CONTROL REGISTER All bits are active high and are reset on power-up or reset command, except PLL enable, which defaults to enabled (high) on power-up or reset. PLL Enable: When this bit is set to a one, the signals used to program and read the PLL are enabled.

  • Page 15: Rl1_User_Switch

    Switch Setting FIGURE 5 PMC-BISERIAL-III RL1 USER SWITCH PORT Switch Setting: The user switch is read through this port. The bits are read as the lowest byte in the port. Access the read-only port as a long word and mask off the undefined bits.

  • Page 16: Rl1_Chan_0-7_Control

    Receive FIFO Reset Transmit FIFO Reset FIGURE 6 PMC-BISERIAL-III RL1 CHANNEL CONTROL REGISTER Transmit/Receive FIFO Reset: When these bits are set to a one, the transmit and/or receive FIFOs will be reset. When these bits are zero, normal FIFO operation is enabled.
  • Page 17 Transmit / Receive DMA Priority Arbitration Enable: When this bit is set to a one, the corresponding DMA channel will get priority if it is near the limit of its FIFO (almost empty for the TX or almost full for the RX). These limits are derived from the programmable counts in the RL1_CHAN_0-7_TX_AMT_LVL and RL1_CHAN_0- 7_RX_AFL_LVL registers.

  • Page 18: Rl1_Chan_0-7_Status

    Transmit FIFO Empty FIGURE 7 PMC-BISERIAL-III RL1 CHANNEL STATUS PORT Transmit FIFO Empty: When a one is read, the transmit data FIFO contains no data; when a zero is read, there is at least one data word in the FIFO.
  • Page 19 empty. When this bit is a zero, it indicates that there is no data in this holding register. Receive FIFO Empty: When a one is read, the receive data FIFO contains no data; when a zero is read, there is at least one data word in the FIFO. Receive FIFO Almost Full: When a one is read, the number of data words in the receive data FIFO is greater or equal to the value written to the RL1_CHAN_RX_AFL_LVL register;...
  • Page 20 writing back to the Status register with a one in the appropriate bit position. Write/Read DMA Interrupt Occurred: When a one is read, a write/read DMA interrupt is latched. This indicates that the scatter-gather list for the current write or read DMA has completed, but the associated interrupt has yet to be processed.

  • Page 21: Rl1_Chan_0-7_Wr_Dma_Pntr

    11-0 TX Data Words Stored FIGURE 9 PMC-BISERIAL-III RL1 TX FIFO DATA COUNT PORT This read-only register port reports the number of 32-bit data words in the transmit FIFO and data holding register (currently a maximum of 0x401). Embedded Solutions...

  • Page 22: Rl1_Chan_0-7_Rd_Dma_Pntr

    Spare 11-0 RX Data Words Stored FIGURE 11 PMC-BISERIAL-III RL1 RX FIFO DATA COUNT PORT This read-only register port reports the number of 32-bit data words in the receive FIFO and data pipeline (currently a maximum of 0x404). Embedded Solutions...

  • Page 23: Rl1_Chan_0-7_Fifo

    TX FIFO Almost-Empty Level FIGURE 13 PMC-BISERIAL-III RL1 TX ALMOST EMPTY LEVEL REGISTER This read/write port accesses the transmitter almost-empty level register. When the number of data words in the transmit data FIFO is equal or less than this value, the almost-empty status bit will be set.

  • Page 24: Rl1_Chan_0-7_Tx_Control

    Transmitter Enabled (read only) FIGURE 15 PMC-BISERIAL-III RL1 TX CONTROL REGISTER Transmitter Enabled: When a one is read, the transmit state-machine is enabled and either a message is in progress or it is waiting for data to be written to the transmit FIFO;...

  • Page 25: Rl1_Chan_0-7_Rx_Control

    Receiver Enabled (read only) FIGURE 16 PMC-BISERIAL-III RL1 RX CONTROL REGISTER Receiver Enabled: When a one is read, the Receive state-machine is enabled and either a message is in progress or it is waiting for a message to begin; when a zero is read, the state-machine is disabled.
  • Page 26 Receive FIFO Overflow Interrupt Enable: When this bit is set to a one, the receive FIFO overflow interrupt is enabled. An interrupt will be asserted, provided the master interrupt is enabled when an attempt is made to write to a full receive FIFO. When this bit is zero, the receive FIFO overflow interrupt is disabled.

  • Page 27: Figure 5 Figure

    TX Start FIGURE 17 PMC-BISERIAL-III RL1 TX START LATCH TX Start: When this bit is set to a one, the transmit state-machine will be enabled. When this bit is zero the state-machine will be disabled. The value of the TX start bit is read from the TX_CONTROL register bit 0.

  • Page 28: Rl1_Chan_0-7_Rx_Byte_Count

    15-0 RX Bytes Received FIGURE 19 PMC-BISERIAL-III RL1 RX BYTE COUNT PORT RX Bytes Received: This field represents the number of bytes received in the last message. The value will remain valid until the end of a subsequent message. The Receive Done Interrupt can be used to indicate when this value has been updated.

  • Page 29: Loop-Back

    Loop-back The Engineering kit has reference software, which includes external loop-back tests. The PMC-BISERIAL-III RL1 has a 68 pin SCSI II front panel connector. The tests require an external cable with the following pins connected. Full-Duplex Loop-Back Signal From Signal...

  • Page 30: Pmc Pci Pn1 Interface Pin Assignment

    The figure below gives the pin assignments for the PMC Module PCI Pn1 Interface on the PMC-BISERIAL-III RL1. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification but not needed by this design.

  • Page 31: Pmc Pci Pn2 Interface Pin Assignment

    The figure below gives the pin assignments for the PMC Module PCI Pn2 Interface on the PMC-BISERIAL-III RL1. See the User Manual for your carrier board for more information. Unused pins may be assigned by the specification but not needed by this design.

  • Page 32: Front Panel I/O Pin Assignment

    Front Panel I/O Pin Assignment The figure below gives the pin assignments for the PMC Module I/O Interface on the PMC-BiSerial-III RL1. For a customized version, or other options, contact Dynamic Engineering. IO_0p (TX0 DATA +) IO_0m (TX0 DATA -)

  • Page 33: Applications Guide

    Applications Guide Interfacing Some general interfacing guidelines are presented below. Do not hesitate to contact the factory if you need more assistance. Proper ESD handling procedures must be followed when handling the PMC-BISERIAL- III RL1. The card is shipped in an anti-static, shielded bag. The card should remain in the bag until ready for use.

  • Page 34: Construction And Reliability

    Celsius. Thermal Considerations The PMC-BISERIAL-III RL1 design consists of CMOS circuits. The power dissipation due to internal circuitry is very low. It is possible to create higher power dissipation with the externally connected logic.

  • Page 35: Service Policy

    For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty.

  • Page 36: Specifications

    Specifications Host Interface: [PMC] PCI Mezzanine Card – 32-bit, 33 MHz Serial Interfaces: Sixteen UART interfaces (one in and one out per channel). 8-bit data, LSB first, one start-bit, one or two stop-bits and optional parity TX Bit-rates generated: Up to 10 Mbits/second for TX and RX, clock references supplied by the on-board PLL (clock A or B independently selectable), independent divisors from 1 to 32 (even numbers only).

  • Page 37: Order Information

    HDEcabl68 - 68 I/O twisted pair cable http://www.dyneng.com/HDEcabl68.html Technical Documentation, 1. PMC-BiSerial-III Schematic 2. PMC-BISERIAL-III RL1 Driver software and user application. Data sheet reprints are available from the manufacturer’s web site -ROHS Add for ROHS processing. Standard soldering and parts used otherwise.

Table of Contents