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Related Manuals for Dynamic Engineering IP-429-II
Summary of Contents for Dynamic Engineering IP-429-II
- Page 1 DYNAMIC ENGINEERING 150 DuBois St Suite C, Santa Cruz, CA 95060 831-457-8891 Fax 831-457-4793 Web Page http://www.dyneng.com E-Mail sales@dyneng.com Est. 1988 User Manual IP-429-II ARINC 429 Interface IP Module Revision A1 Corresponding Hardware: 10-2007-0501/2...
- Page 2 IP429-II Dynamic Engineering has made every effort to ensure that ARINC 429 Interface this manual is accurate and complete. Still, the company IP Module...
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Page 3: Table Of Contents
Table of Contents PRODUCT DESCRIPTION THEORY OF OPERATION ADDRESS MAP PROGRAMMING Register Definitions IP429II_BASE_REG0 IP429II_BASE_REG1 IP429II_BASE_REG2 IP429II_BASE_REG3 IP429II_VECTOR IP429II_STATUS0 IP429II_STATUS1 IP429II_Parallel IP429_Encoder/Decoder IP429_CHx_CNTL IP429_CHXX_TS Interrupts ID PROM LOOP-BACK IP MODULE LOGIC INTERFACE PIN ASSIGNMENT IP MODULE IO INTERFACE PIN ASSIGNMENT APPLICATIONS GUIDE Interfacing Construction and Reliability... - Page 4 Thermal Considerations WARRANTY AND REPAIR Service Policy Out of Warranty Repairs For Service Contact: SPECIFICATIONS ORDER INFORMATION Embedded Solutions Page 4...
- Page 5 List of Figures FIGURE 1 IP-429 INTERNAL ADDRESS MAP FIGURE 2 IP-429 CONTROL REGISTER 0 BIT MAP FIGURE 3 IP-429 CONTROL REGISTER 1 BIT MAP FIGURE 4 IP-429 CONTROL REGISTER 2 BIT MAP FIGURE 5 IP-429 CONTROL REGISTER 3 BIT MAP FIGURE 6 IP-429 STATUS REGISTER 0 BIT MAP FIGURE 7...
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Page 6: Product Description
There are many devices supporting the 429 bus - printers, instrumentation, sensors and more. IP-429-II makes it easy to gain access to the ARINC 429 bus. Just connect; program a few registers and use like an IO device. Reference software, schematics and debugging aides are available in the Engineering Kit. - Page 7 Word and byte operations are supported (please refer to the memory map). IP-429-II conforms to the VITA standard. This guarantees compatibility with multiple IP Carrier boards. Because the IP may be mounted on different form factors, while maintaining plug and software compatibility, system prototyping may be done on one IP Carrier board, with final system implementation on a different one.
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Page 8: Theory Of Operation
The ‘3282 data sheet is available on-line from the IP-429 webpage. IP-429-II is a part of the IP Module family of I/O products. It meets the IP Module VITA Standard. Contact VITA for a copy of this specification. It is assumed that the reader is at least casually familiar with this document and logic design. - Page 9 To receive data another transmitter in the system sends data on the bus, which is connected, to the IP-429. There are up to eight receive channels per IP-429-II and each channel can be connected to a different ARINC 429 bus. The Receiver channels are controlled in pairs for the clock speed.
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Page 10: Address Map
Address Map IO Space Function Offset Width Type // IP 429 relative addresses // #define IP429II_BASE_REG0 0x00 // byte on word boundary #define IP429II_BASE_REG1 0x02 // byte on word boundary #define IP429II_BASE_REG2 0x04 // byte on word boundary #define IP429II_BASE_REG3 0x06 // byte on word boundary #define IP428II_VECTOR... -
Page 11: Figure 1 Ip-429 Internal Address Map
32 ó 16 conversion. All Dynamic Engineering carriers have this feature. IP-429-II can have up to 4 of the encoder/decoder “chips” installed. The –1 version has device 1 installed , -2 has both device 0 and device 1 and so forth. The names for the decodes above have the chip number followed by the port within the chip and the function. -
Page 12: Programming
[PCI, PCIe etc]. Dynamic Engineering drivers take care of the system level interaction and provide an easy to use platform to write your user level software. The driver comes with “Userap”... -
Page 13: Register Definitions
Register Definitions IP429II_BASE_REG0 [$00 429 Control Register Port read/write CONTROL REGISTER 0 DATA BIT DESCRIPTION Send4 0 = tx disabled, 1 = enabled ch3 Send3 0 = tx disabled, 1 = enabled ch2 Send2 0 = tx disabled, 1 = enabled ch1 Send1 0 = tx disabled, 1 = enabled ch0 spare... -
Page 14: Ip429Ii_Base_Reg1
IP429II_BASE_REG1 $02 429 Control Register Port read/write CONTROL REGISTER 1 DATA BIT DESCRIPTION /RESET4 reset, 1 = enabled /RESET3 /RESET2 /RESET1 /DBCEN4 1 = force parity, 0 = normal /DBCEN3 /DBCEN2 /DBCEN1 FIGURE 3 IP-429 CONTROL REGISTER 1 BIT MAP /DBCENx is used to force Parity to be inserted into the data stream. -
Page 15: Figure 4 Ip-429 Control Register 2 Bit Map
IP429II_BASE_REG2 $04 429 Control Register Port read/write CONTROL REGISTER 2 DATA BIT DESCRIPTION spare spare spare spare Hi/_LO_4 1 = 100Khz, 0 = 12.5 KHz. Hi/_LO_3 Hi/_LO_2 Hi/_LO_1 FIGURE 4 IP-429 CONTROL REGISTER 2 BIT MAP The transmit speed port is used to select the transmit speed for each of the ports installed. -
Page 16: Ip429Ii_Vector
Tx Int En X is used to enable or disable the interrupt associated with the transmit device installed. Devices not populated on the board should be masked off. 1 = enabled and 0 = disabled for the interrupt. Default = 0. The leading edge of the TXRx status line from the “3282”... -
Page 17: Ip429Ii_Status0
IP429II_STATUS0 [$0A 429 Control Register Port read only CONTROL REGISTER 1 DATA BIT DESCRIPTION DR2 device 4 1 = data ready, 0 = no data DR1 device 4 DR2 device 3 DR1 device 3 DR2 device 2 DR1 device 2 DR2 device 1 DR1 device 1 FIGURE 6... -
Page 18: Ip429Ii_Status1
IP429II_STATUS1 [$0C 429 Control Register Port read only CONTROL REGISTER 1 DATA BIT DESCRIPTION undefined undefined undefined undefined TXR4 TXR3 TXR2 TXR1 FIGURE 7 IP-429 STATUS REGISTER 1 BIT MAP The TXRx bits are the Transmitter Ready bits driven from the “3282”. When high the bits indicate that the transmitter is ready to receive data. -
Page 19: Ip429Ii_Parallel
IP429II_Parallel $0E 429 Control Register Port read/write CONTROL REGISTER Parallel Port DATA BIT DESCRIPTION 15-8 read-back of lower 7 bits PI_7 – read-back “cable side” PI_6 PI_5 PI_4 PIO_3 PIO_2 PIO_1 PIO_0 FIGURE 8 IP-429 CONTROL REGISTER 0 BIT MAP The PIO port consists of read only and read-writeable bits. -
Page 20: Ip429_Encoder/Decoder
IP429_Encoder/Decoder #define IP429II_OE0_DEV1_L 0x40 // read from Device 1 port 1 lower half #define IP429II_OE0_DEV1_U 0x42 // read from Device 1 port 1 upper half #define IP429II_OE1_DEV1_L 0x44 // read from Device 1 port 2 lower half #define IP429II_OE1_DEV1_U 0x46 // read from Device 1 port 2 upper half #define IP429II_LD1_DEV1 0x48... -
Page 21: Ip429_Chx_Cntl
IP429_CHx_CNTL CONTROL REGISTER 0 DATA BIT DESCRIPTION WLSEL RCVSEL TXSEL PARCK SDEN2 SDEN1 /SLFTST PAREN UNUSED UNUSED UNUSED UNUSED FIGURE 9 IP-429 3282 CONTROL REGISTER BIT MAP The details of programming the 3282 can be found in the DDC-ILC DATA Device Corporation Data Book. - Page 22 very briefly mentioned on page 6 of the DDC-03282 data sheet. SDEN1,2 X1,2 Y1,2 S/D code check enable and check bits. If SDENx is set to 1 then the corresponding receiver checks for the X and Y bits to match. If set to 0 then all properly formatted data is received.
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Page 23: Ip429_Chxx_Ts
IP429_CHXX_TS The Time Stamp registers are now accessed in the IO space. Be sure to use the correct offset. There are eight (8) registers each used to store one 32 bit Time Tag. The receiver number is the number assigned to each receiver on the board. Please refer to the chart below. -
Page 24: Interrupts
Interrupts All IP Module interrupts are vectored. The vector from the IP-429 comes from a vector register loaded as part of the initialization process. The vector register can be programmed to any 8 bit value. The default value is $FF which is sometimes not a valid user vector. -
Page 25: Id Prom
+ $80. Dynamic Engineering parent drivers use the ID PROM automatically to instantiate the correct child driver for a particular slot. Standard data in the ID PROM on the IP-429-II is shown in the figure below. For more information on IP ID PROM’s refer to the IP Module Logic Interface Specification, available from Dynamic Engineering. -
Page 26: Loop-Back
429-II Loop-Back can be performed. The following table shows the connections used for the Dynamic Engineering test software. There are 4 possible devices and all are shown. The first set is for Device 1. The first entry is for the A signal and the second for the B. -
Page 27: Ip Module Logic Interface Pin Assignment
IP Module Logic Interface Pin Assignment The figure below gives the pin assignments for the IP Module Logic Interface on the IP- 429. Pins marked n/c below are defined by the specification, but not used on the IP-429. Also see the User Manual for your carrier board for more information. Reset* R/W* IDSEL*... -
Page 28: Ip Module Io Interface Pin Assignment
IP Module IO Interface Pin Assignment The figure below gives the pin assignments for the IP Module IO Interface on the IP- 429. Also see the User Manual for your carrier board for more information. Dev1Ch1_RXA Dev3_TXA Dev1Ch1_RXB Dev3_TXB Dev1Ch2_RXA Dev4Ch1_RXA Dev1CH2_RXB Dev4Ch1_RXB... -
Page 29: Applications Guide
The terminal block mounts on standard DIN rails. [http://www.dyneng.com/HDRterm50.html Carriers – Dynamic Engineering has carriers for PCI, cPCI and PC104p. Check for PCIe and VPX. User the Java menu tabs to navigate to the format [cPCI etc] and then the function on our website. -
Page 30: Construction And Reliability
Construction and Reliability IP Modules were conceived and engineered for rugged industrial environments. IP-429- II is constructed out of 0.062 inch thick high temp FR4 material. Through hole and surface mounting of components are used. IC sockets use gold plated screw machine pins. High insertion and removal forces are required, which assists in the retention of components. -
Page 31: Thermal Considerations
For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller. Products returned to Dynamic Engineering for repair by other than the original customer will be treated as out-of-warranty. -
Page 32: For Service Contact
For Service Contact: Customer Service Department Dynamic Engineering 150 DuBois St Suite C Santa Cruz, CA 95060 831-457-8891 831-457-4793 fax Internet Address support@dyneng.com Embedded Solutions Page 32... -
Page 33: Specifications
Specifications Logic Interface: IP Module Logic Interface ARINC Interface: 429, other interfaces possible CLK rates supported: 100, 12-14.5 KHz., Software Interface: Control Register, ID PROM, Vector Register, and Status Port Initialization: Hardware Reset forces all registers to 0. Software Reset Command resets the control register, and FIFO’s. Access Modes: Word or Byte in I/O Word in ID Space... -
Page 34: Order Information
Not recommended for new designs, provided for backward compatibility. Tools for IP-429-x IP-Debug-Bus - IP Bus interface extender http://www.dyneng.com/ipdbgbus.html IP--Debug-IO - IO connector breakout http://www.dyneng.com/ipdbgio.html HDRterm50 50 position terminal block breakout from ribbon cable http://www.dyneng.com/HDRterm50.html All information provided is Copyright Dynamic Engineering Embedded Solutions Page 34...
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