Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual page 27

Write/Read DMA Error Occurred: When a one is read, a write or read DMA error has
been detected. This will occur if there is a target or master abort or if the direction bit in
the next pointer of one of the chaining descriptors is incorrect. A zero indicates that no
write or read DMA error has occurred. These bits are latched and can be cleared by
writing back to the Status register with a one in the appropriate bit position.
Write/Read DMA Interrupt Occurred: When a one is read, a write/read DMA interrupt is
latched. This indicates that the scatter-gather list for the current write or read DMA has
completed, but the associated interrupt has yet to be processed. A zero indicates that
no write or read DMA interrupt is pending.
Tx IDLE is set when the state-machine is in the idle state. When lower clock rates are
used it may take a while to clean-up and return to the idle state. If SW has cleared the
start bit to terminate the data transfer; SW can use the IDLE bit to determine when the
HW has completed its task and returned.
BO and BI Idle are Burst Out and Burst In IDLE state status for the Receive and
Transmit DMA actions. The bits will be 1 when in the IDLE state and 0 when
processing a DMA. A new DMA should not be launched until the State machine is back
in the IDLE state. Please note that the direction implied in the name has to do with the
DMA direction – Burst data into the card for Transmit and burst data out of the card for
Receive.
Local Interrupt is the masked combined interrupt status for the channel not including
DMA. The status is before the master interrupt enable for the channel.
Interrupt Status is the combined Local Interrupt with DMA and the master interrupt
enable. If this bit is set this channel has a pending interrupt request.
EXT FIFO Empty: When a one is read, the discrete FIFO(s) contains no data, when a
zero is read, there is at least one word in the FIFO.
EXT FIFO Full: When a one is read, the discrete FIFO(s) is full; when a zero is read,
there is room for at least one more word in the FIFO.
Please note: the EXT FIFO's have a separate reset bit to clear those devices. Since
there is a pipeline involved, the resets should be applied together for best results.
Transmitter Idle is set when the Transmit State-Machine is in the Idle state. The state-
machine operates at the PLLA rate and may take a few states to return to Idle from a
disable condition. The Idle state can be used to determine when the State-machine is
ready to be recommanded.
TxAELvlIntLat: When set the Tx Data FIFO has become almost Empty based on the
Embedded Solutions Page 27