Specifications - Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual

Specifications

Logic Interface:
Digital Parallel IO:
Digital Serial IO:
DIP Switch:
CLK rates supported:
Software Interface:
Initialization:
Access Modes:
Access Time:
Interrupt:
Onboard Options:
Interface Options:
Dimensions:
Construction:
Power:
Weight:
PCIe 1-4 lanes. 4 lanes recommended
LVDS IO
2 bit serial with sync and reference clock.. Data
valid on falling edge of clock. 76.636 MHz for initial
target design.
DipSwitch supplied for board identification and
other user purposes.
PLLA is programmed to select Transmit Clock rate.
For loop-back and alternate HW implementations.
PLLB, C, D reserved for new applications.
Control Registers, IO registers, IO Read-Back
registers, FIFO. R/W, 32 bit boundaries.
Programming procedure documented in this
manual
LW to registers, read-write to most registers
Frame to TRDY 121 nS [4 PCI clocks] or burst
mode DMA – 1 word per PCI clock transferred.
Each port has independently programmable
interrupt sources, DMA interrupts included.
All Options are Software Programmable
37 Pin DB connector at front bezel.
Standard 1/2 length PCIe module.
Multi-Layer Printed Circuit, Through Hole and
Surface Mount Components.
+12 and +3.3 used from PCIe interface. No
secondary power supply connections required. 1.2,
2.5 and 5V developed locally.
TBD oz
Embedded Solutions Page 43