Channel Address Map; Figure 5 Pciebiserialdb37Ba22 Channel Address Map - Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual

Channel Address Map

Function
#define CHAN_CNTRL
#define CHAN_STATUS
#define CHAN_INT_CLEAR
#define CHAN_WR_DMA_PNTR
#define CHAN_TX_FIFO_COUNT 0x00000008 // 2 Tx FIFO count read port
#define CHAN_RD_DMA_PNTR
#define CHAN_RX_FIFO_COUNT 0x0000000C // 3 Rx FIFO count read port
#define CHAN_FIFO
#define CHAN_TX_AMT
and pulsed interrupt
#define CHAN_RX_AFL
#define CHAN_READY_CNT
#define CHAN_FRAME_REF
triggers
#define CHAN_LINE_LENGTH
#define CHAN_IDLE_LENGTH
#define CHAN_FRAME_LENGTH 0x00000034 // 13 Number of lines in a frame
#define CHAN_TX_PreAmblePat
#define CHAN_TX_PreAmbleLen 0x0000003C // 15 PreAmble number of Pixels
#define CHAN_TX_SyncPat
#define CHAN_TX_SyncLen
#define CHAN_TX_IdlePat
#define CHAN_TX_DataPat

Figure 5 PcieBiSerialDb37BA22 Channel Address Map

Offset from Channel Base Address
0x00000000 // 0 General control register
0x00000004 // 1 Interrupt status port
0x00000004 // 1 Interrupt clear port
0x00000008 // 2 Write DMA dpr physical PCI address register
0x0000000C // 3 Read DMA dpr physical PCI address register
0x00000010 // 4 FIFO offset for single word access R/W
0x00000014 // 5 Tx almost empty count register - used for Urgent
0x00000018 // 6 Rx almost full count register
0x00000024 // 9 Amount of data in pipeline before Tx can start
0x00000028 // 10 Count representing time between frame start
0x0000002C // 11 Number of pixels in a line
0x00000030 // 12 Number of idles at end of line
0x00000038 // 14 PreAmble Control Word
0x00000040 // 16 Sync Control Word
0x00000044 // 17 Sync Number of Pixels
0x00000048 // 18 Idle Control Word
0x0000004C // 19 Data Control Word
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