Figure 3 Pciebiserialdb37Ba22 Image Diagram - Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual

changing on the rising edge, and stable on the falling edge.
The transmit rate is programmable for the BA22. PLL channel A is programmed to
73.636 MHz for a 73.636 MHz. output rate.
Sync programmable both for pattern and number of pixels. In addition a PreAmble is
provided again with programmable pattern and number of pixels. Master Frame Sync
=> PreAmble => Sync => Data/IDLE... complete Frame. If the number of PreAmble
Pixels is zero the HW will automatically skip to the Sync unless that is also zero pixels in
which case it starts with the Data Control pattern.
Some camera interfaces use a 1 pixel sync followed by some number of IDLE
characters to form a sync pattern. In this case the PreAmble is programmed as the
SYNC, the SYNC as the IDLE pattern and then DATA and IDLE as normal. The
PreAmble length would be 1 and the Sync length 3 or whatever the camera interface
requires.
LINE LENGTH IDLE
IMAGE AREA
BLANKING

Figure 3 PCIEBISERIALDB37BA22 Image Diagram

The Image Transfer Area is controlled by programming the number of pixels per line
[Line Length], the number of pixel times at the end of a line [Idle Length], the number of
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