Ba22_Chan_Rx_Fifo_Count; Ba22_Chan_Fifo; Figure 15 Pciebiserialdb37Ba22 Rx Fifo Data Count Port; Figure 16 Pciebiserialdb37Ba22 Rx/Tx Fifo Port - Dynamic Engineering PCIeBiSerialDb37-BA22 User Manual

Notes:
1. Writing a zero to this port will abort a write DMA in progress.
2. End of chain should not be set for the address written to the DMA Pointer
Address Register. End of chain should be set when the descriptor follows the
last length parameter.
3. The Direction should be set to '1' for Burst Out DMA in all chaining descriptor
locations.

BA22_CHAN_RX_FIFO_COUNT

[0xC] RX [Master] FIFO data count (read only)
Data Bit

Figure 15 PcieBiSerialDb37BA22 RX FIFO data count Port

This read-only register port reports the number of 32-bit data words in the Receive FIFO
plus pipeline. The maximum count is the FIFO size plus 4.

BA22_CHAN_FIFO

[0x10] Write TX/Read RX FIFO Port
Data Bit

Figure 16 PcieBiSerialDb37BA22 RX/TX FIFO Port

This port is used to make single-word accesses to and from the FIFO. Data read from
this port will no longer be available for DMA transfers. Writing to the port loads the Tx
FIFO, Reading unloads the Rx FIFO.
Two pixels are stored per LW. Pixels are 14 bits. Upper two bits per pixel for transmit
are ignored. Upper two bits per pixel for Rx are reserved.
D31,D30, D29-D16, D15, D14 D13-0 The data transmitted and received for the D29-16
and D13-0 can be reversed orderwise to match your system memory situation. See the
Data_Order control bits. The receive data has an extra feature. Bit 15/31 is set for the
pixel corresponding to one having the frame bit set.
RX FIFO Data Count Port
31-0
RX and TX FIFO Port
31-0
Description
RX Data Words Stored
Description
FIFO data word
Embedded Solutions Page 31