Aaeon GENE-8310 Manual page 53

Intel celeron m processor subcompact board 18/24-bit dual-channel lvds ethernet, 2 channel audio & mini pci
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S u b C o m p a c t B o a r d
Set_Logic_Device proc near
push ax
push cx
xchg al,cl
mov cl,07h
call Superio_Set_Reg
pop cx
pop ax
ret
Set_Logic_Device endp
;Select 02Eh->Index Port, 02Fh->Data Port
Cfg_Port DB 087h,001h,055h,055h
DW 02Eh,02Fh
END Main
Note: Interrupt level mapping
0Fh-Dh: not valid
0Ch: IRQ12
.
.
03h: IRQ3
02h: not valid
01h: IRQ1
00h: no interrupt selected
Appendix A Programming the Watchdog Timer
G E N E - 8 3 1 0
A-10

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