Flash Memory Erase - ST STM32F101xx series Programming Manual

Reading/programming the embedded Flash memory
Standard programming
In this mode the CPU programs the main Flash memory by performing standard half-word
write operations. The PG bit in the FLASH_CR register must be set. FPEC preliminarily
reads the value at the addressed main Flash memory location and checks that it has been
erased. If not, the program operation is skipped and a warning is issued by the PGERR bit in
FLASH_SR register (the only exception to this is when 0x0000 is programmed. In this case,
the location is correctly programmed to 0x0000 and the PGERR bit is not set). If the
addressed main Flash memory location is write-protected by the FLASH_WRPR register,
the program operation is skipped and a warning is issued by the WRPRTERR bit in the
FLASH_SR register. The end of the program operation is indicated by the EOP bit in the
FLASH_SR register.
The main Flash memory programming sequence in standard mode is as follows:
●
Check that no main Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
●
Set the PG bit in the FLASH_CR register.
●
Perform the data write (half-word) at the desired address.
●
Wait for the BSY bit to be reset.
●
Read the programmed value and verify.
Note: The registers are not accessible in write mode when the BSY bit of the FLASH_SR register
is set.
2.3.4

Flash memory erase

The Flash memory can be erased page by page or completely (Mass Erase).
Page Erase
A page of the Flash memory can be erased using the Page Erase feature of the FPEC. To
erase a page, the procedure below should be followed:
●
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_CR register
●
Set the PER bit in the FLASH_CR register
●
Program the FLASH_AR register to select a page to erase
●
Set the STRT bit in the FLASH_CR register
●
Wait for the BSY bit to be reset
●
Read the erased page and verify
14/31 Doc ID 17863 Rev 1
PM0075