Fpec Key Register (Flash_Keyr); Flash Optkey Register (Flash_Optkeyr) - ST STM32F101xx series Programming Manual
Stm32f10xxx flash memory microcontrollers
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Also See for STM32F101xx series:
- Reference manual (1096 pages) ,
- Reference manual (959 pages)
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Register descriptions
Bit 4 PRFTBE: Prefetch buffer enable
Bit 3 HLFCYA: Flash half cycle access enable
Bits 2:0 LATENCY: Latency
3.2
FPEC key register (FLASH_KEYR)
Address offset: 0x04
Reset value: xxxx xxxx
31
30
29
w
w
w
15
14
13
w
w
w
Note:
These bits are all write-only and will return a 0 when read.
Bits 31:0 FKEYR: FPEC key
3.3
Flash OPTKEY register (FLASH_OPTKEYR)
Address offset: 0x08
Reset value: xxxx xxxx
31
30
29
w
w
w
15
14
13
w
w
w
Note:
These bits are all write-only and will return a 0 when read.
Bits 31:0
OPTKEYR: Option byte key
24/31
0: Prefetch is disabled
1: Prefetch is enabled
0: Half cycle is disabled
1: Half cycle is enabled
These bits represent the ratio of the SYSCLK (system clock) period to the Flash access
time.
000 Zero wait state, if 0 < SYSCLK≤ 24 MHz
001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
These bits represent the keys to unlock the FPEC.
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
These bits represent the keys to unlock the OPTWRE.
24
23
22
FKEYR[31:16]
w
w
w
8
7
6
FKEYR[15:0]
w
w
w
24
23
22
OPTKEYR[31:16]
w
w
w
8
7
6
OPTKEYR[15:0]
w
w
w
Doc ID 17863 Rev 1
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
PM0075
17
16
w
w
1
0
w
w
17
16
w
w
1
0
w
w
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