Digilent Nexys4 DDR Reference Manual page 21

Nexys4 DDR™ FPGA Board Reference Manual
11 Pmod Ports
The Pmod ports are arranged in a 2x6 right-angle, and are 100-mil female connectors that mate with standard 2x6
pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and
11), and eight logic signals, as shown in Figure 20. The VCC and Ground pins can deliver up to 1A of current. Pmod
data signals are not matched pairs, and they are routed using best-available tracks without impedance control or
delay matching. Pin assignments for the Pmod I/O connected to the FPGA are shown in Table 5.
Pmod JA
JA1: C17
JA2: D18
JA3: E18
JA4: G17
JA7: D17
JA8: E17
JA9: F18
JA10: G18
Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors
to add ready-made functions like A/D's, D/A's, motor drivers, sensors, as well as other functions. See
www.digilentinc.com for more information.
11.1 Dual Analog/Digital Pmod
The on-board Pmod expansion connector labeled "JXADC" is wired to the auxiliary analog input pins of the FPGA.
Depending on the configuration, this connector can be used to input differential analog signals to the analog-to-
digital converter inside of the Artix-7 (XADC). Any or all pairs in the connector can be configured either as analog
input or digital input-output.
The Dual Analog/Digital Pmod on the Nexys4 DDR differs from the rest in the routing of its traces. The eight data
signals are grouped into four pairs, with the pairs routed closely coupled for better analog noise immunity.
Furthermore, each pair has a partially loaded anti-alias filter laid out on the PCB. The filter does not have
capacitors C60-C63. In designs where such filters are desired, the capacitors can be manually loaded by the user.
NOTE: The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals.
The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1
MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The
XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also
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VCC GND 8 signals
Pin 6
Pin 12
Figure 20. PMOD ports; front view, as loaded on PCB.
Pmod JB Pmod JC Pmod JD
JB1: D14 JC1: K1 JD1: H4
JB2: F16 JC2: F6 JD2: H1
JB3: G16 JC3: J2 JD3: G1
JB4: H14 JC4: G6 JD4: G3
JB7: E16 JC7: E7 JD7: H2
JB8: F13 JC8: J3 JD8: G4
JB9: G13 JC9: J4 JD9: G2
JB10: H16 JC10: E6 JD10: F3
Table 5. Nexys4 DDR Pmod pin assignments.
Pin 1
Pmod XDAC
JXADC1: A13 (AD3P)
JXADC2: A15 (AD10P)
JXADC3: B16 (AD2P)
JXADC4: B18 (AD11P)
JXADC7: A14 (AD3N)
JXADC8: A16 (AD10N)
JXADC9: B17 (AD2N)
JXADC10: A18 (AD11N)
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