Digilent Nexys4 DDR Reference Manual page 17

Nexys4 DDR™ FPGA Board Reference Manual
counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse
and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
Horizontal
Pixel
Counter
CLK
10 Basic I/O
The Nexys4 DDR board includes two tri-color LEDs, sixteen slide switches, six push buttons, sixteen individual LEDs,
and an eight-digit seven-segment display, as shown in Figure 16. The pushbuttons and slide switches are
connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could
occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). The five
pushbuttons arranged in a plus-sign configuration are "momentary" switches that normally generate a low output
when they are at rest, and a high output only when they are pressed. The red pushbutton labeled "CPU RESET," on
the other hand, generates a high output when at rest and a low output when pressed. The CPU RESET button is
intended to be used in EDK designs to reset the processor, but you can also use it as a general purpose
pushbutton. Slide switches generate constant high or low inputs depending on their position.
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Zero
Set
Detect
Horizontal
Synch
3.84us
Reset
Detect
Figure 15. VGA display controller block diagram.
Zero
Set
CE
Detect
Vertical
Counter
64us
Reset
Detect
HS
VS
Vertical
Synch
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