Digilent Nexys4 DDR Reference Manual page 16

Nexys4 DDR™ FPGA Board Reference Manual
pixel 0,0
640 pixels per row are displayed
during forward beam trace
Display Surface
pixel 479,0
Stable current ramp - information is
displayed during this time
Current
waveform
through
horizontal
defletion
coil
Horizontal display time
HS
"front porch"
information. The VS signal defines the "refresh" frequency of the display, or the frequency at which all information
on the display is redrawn. The minimum refresh frequency is a function of the display's phosphor and electron
beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be
displayed at a given refresh frequency defines the horizontal "retrace" frequency. For a 640-pixel by 480-row
display using a 25 MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in Figure 14 can be derived.
Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync pulse
times during which information cannot be displayed) are based on observations taken from actual VGA displays.
Figure 14. Signal timings for a 640-pixel by 480 row display using a 25 MHz pixel clock and 60 Hz vertical refresh.
A VGA controller circuit, such as the one diagramed in Figure 15, decodes the output of a horizontal-sync counter
driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a
given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to
generate VS signal timings, and you can use this counter to locate any given row. These two continually running
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pixel 0,639
Retrace - no
information
displayed
during this
time
pixel 479,639
Total horizontal time
retrace
Horizontal sync signal sets
retrace frequency "back porch"
T
fp
T
pw
Symbol Parameter
Time
T S
Sync pulse 16.7ms
T disp
Display time 15.36ms
T pw
Pulse width 64 us
T fp
Front porch 320 us
T bp
Back porch 928 us
displays use from 240 to 1200 rows and
from 320 to 1600 columns. The overall
size of a display and the number of rows
and columns determines the size of each
pixel.
Video data typically comes from a video
refresh memory; with one or more bytes
assigned to each pixel location (the
Nexys4 DDR uses 12 bits per pixel). The
controller must index into video memory
as the beams move across the display, and
retrieve and apply video data to the
display at precisely the time the electron
beam is moving across a given pixel.
A VGA controller circuit must generate the
time
HS and VS timings signals and coordinate
the delivery of video data based on the
time
pixel clock. The pixel clock defines the
time available to display one pixel of
T
S
T
disp
T
bp
Vertical Sync Horiz. Sync
Clocks Lines Time
416,800 521 32 us
384,000 480 25.6 us
1,600 2 3.84 us
8,000 10 640 ns
23,200 29 1.92 us
Clks
800
640
96
16
48
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