Digilent Nexys4 DDR Reference Manual page 18

Nexys4 DDR™ FPGA Board Reference Manual
3.3V
BTNL
Buttons
BTNR
BTNU
BTND
BTNC
3.3V
SW0
SW1
SW2
SW3
SW4
Slide
SW5
Switches
SW6
1.8V
SW7
SW8
SW9
SW10
SW11
SW12
SW13
SW14
SW15
CPU Reset
BTNRES
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H17
P17
K15
M17
N14
M18
R18
P18
V17
U17
N17
U16
V16
U14
J15
V15
L16
V14
V12
M13
V11
R15
U13
R17
T18
P14
U18
R13
T8
U8
R16
R10
T13
K16
H6
K13
P15
U12
U11
H15
V10
3.3V
N16
R11
G14
C12
N15
M16
R12
Artix-7
Figure 16. General Purpose I/O devices on the Nexys4 DDR.
LD0
LD1
LD2
J13
LD3
LD4
LD5
LD6
LD7
LD8
LD9
T15
LD10
LD11
T16
LD12
LD13
LD14
LD15
3.3V
AN7
K2
AN6
T14
AN5
J14
T9
J18
J17
T10
CA
CB
CC
CD
CE
T11
CF
L18
CG
DP
Tri-Color
LEDs
R17
LEDs
7-seg
Display
AN4
AN3
AN2
AN1
AN0
5.0V
LD17 LD16
G17
B17
R16
G16
B16
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