Hrdy Behavior During An Hpic Or Hpia Read Cycle In The 16-Bit Multiplexed Mode; Hrdy Behavior During A Data Read Operation In The 16-Bit Multiplexed Mode (Case 1: Hpia Write Cycle Followed By Nonauto-Increment Hpid Read Cycle) - Texas Instruments TMS320C6452 User Manual

Peripheral Architecture
2.7.9.1 HRDY Behavior During 16-bit Multiplexed-Mode Read Operations
Figure 7 shows an HPIC (HCNTL[1:0] = 00b) or HPIA (HCNTL[1:0] = 10b) read cycle. Neither an HPIC
read cycle nor an HPIA read cycle causes HRDY to go low. For this type of access, the state of HHWIL is
ignored, so if a dual halfword access is performed, the same register will be accessed twice.
Figure 7. HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-bit Multiplexed Mode
HCS
HCNTL[1:0]
HR/W
HHWIL
Internal
HSTRB
HD[15:0]
HRDY
Figure 8 includes an HPID read cycle without auto-incrementing. The host writes the memory address
during the HPIA (HCNTL[1:0] = 10b) write cycle, and the host reads the data during the HPID
(HCNTL[1:0] = 11b) read cycle. HRDY goes low for each HPIA halfword access, but HRDY goes low for
only the first halfword access in each HPID read cycle.
Figure 8. HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode
(Case 1: HPIA Write Cycle Followed by Nonauto-increment HPID Read Cycle)
HCS
HAS
HCNTL[1:0 ]
10
HR/W
HHWIL
Internal
HSTRB
HD[15:0 ]
HRDY
Figure 9 includes an auto-increment HPID read cycle. The host writes the memory address while
asserting HCNTL[1:0] = 10b and reads the data while asserting HCNTL[1:0] = 01b. During the first HPID
read cycle, HRDY goes low for only the first halfword access, and subsequent HPID read cycles do not
cause HRDY to go low.
22 Host Port Interface (HPI)
00 or 10
1st halfword
10
1st halfword
00 or 10
11
2nd halfword 1st halfword
SPRUF87A – October 2007 – Revised May 2008
www.ti.com
2nd halfword
11
2nd halfword
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