Sbw-To-Jtag Interface Diagram - Texas Instruments MSP430 User Manual

Interface and Instructions
SBWTDIO
In TMS Slot
SBWTCK
JTAG TAP in
Run Test/Idle
In TDI Slot
In TDO Slot
The advantages of this implementation are:
• Data on TDI and data on TDO are aligned.
• During the TDI_SLOT of the 2-wire interface, SBWTDIO can be used as TCLK input if the JTAG TAP
controller is in its Run-Test/Idle state. For this purpose, the TDI output must be synchronized to its
input as shown in
After power up, as long as the SBW interface is not activated yet, TMS and TDI are set to logic 1 level
internally.
8.2.3.2 TDO Slot
As shown in Figure
in Figure 8-9). The master should release control of the SBWTDIO line based off of the rising edge of
SBWTCK of the TDI cycle. Once the master releases the SBWTDIO line, an internal bus keeper holds the
voltage on the line. The next falling edge of SBWTCK triggers the slave to start driving the bus. The slave
only drives the SBWTDIO line during the low time of the SBWTCK cycle. The master should not enable its
drivers until the slave has released the SBWTDIO line. Therefore, the master could use the rising edge of
the SBWTCK signal as a trigger point to enable its driver.
The low phase of the clock signal supplied on SBWTCK must not be longer than 7 µs, else
Note:
SBW logic is deactivated and must be activated again according to
When using the provided source code example, make sure that interrupts are disabled
during the SBWTCK low phase to ensure accurate timings.
58 MSP430 Programming Via the JTAG Interface
Figure 8-8. SBW-to-JTAG Interface Diagram
Figure 8-10. The synchronization logic is only active in the Run-Test/Idle state.
8-7, the TDO operation is allocated one time slot (see also the detailed timing shown
Reset
SET
D Q
EN
SET
D Q
G
D Q
G
CLR
Section 8.3.1.
SLAU265 – February 2009
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TMS
TDI/TCLK
TCK
TDO