Table of Contents
Advertisement
Introduction
1.3
Functional Block Diagram
Figure 1
is a high-level block diagram showing how the HPI connects a host (left side of figure) and the
processor internal memory (right side of figure). Host activity is asynchronous to the internal processor
clock that drives the HPI. The host functions as a master to the HPI. When HPI resources are temporarily
busy or unavailable, the HPI communicates this to the host by de-asserting the HPI ready (HRDY) output
signal.
The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the host
drives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that the
bus can then be used for data.
The HPI supports two interface modes: HPI16 and HPI32 mode. DSP selects either HPI16 or HPI32 mode
with the help of HPI_WIDTH device configuration pin at reset.
-16-bit multiplexed mode (HPI16): The HPI is called HPI16 when operating as a 16-bit wide host port. This
mode is selected if the HPI_WIDTH configuration pin of the DSP is sampled low at reset. In this mode, a
16-bit data bus (HD[15:0]) carries both addresses and data. HPI16 combines successive 16-bit transfers
to provide 32-bit data to the CPU. The halfword identification line (HHWIL) input is used on the HPI16 to
identify the first or second half word of a word transfer.
-32-bit multiplexed mode (HPI32): HPI operates in this mode as a 32-bit wide host port. This mode is
selected if the HPI_WIDTH configuration pin of the DSP is sampled high at reset. In this mode, a 32-bit
data bus (HD[31:0]) carries both addresses and data. HHWIL is not applicable for HPI32 mode.
The HPI contains two HPIAs (HPIAR and HPIAW), which can be used as separate address registers for
read accesses and write accesses(for details, see
A control register (HPIC) is accessible by the CPU and the host. The CPU uses HPIC to send an interrupt
request to the host, to clear an interrupt request from the host, and to configure and monitor the HPI.
Data flow between the host and the HPI uses a temporary storage register, the 32-bit data register (HPID).
Data arriving from the host is held in HPID until the data can be stored elsewhere in the processor. Data
to be sent to the host is held in HPID until the HPI is ready to perform the transfer. When address
auto-incrementing is used, read and write FIFOs are used to store burst data. If auto-incrementing is not
used, the FIFO memory acts as a single register (only one location is used).
Note: To manage data transfers between HPID and the internal memory, the DSP contains dedicated HPI
DMA logic. The HPI DMA logic is not programmable. It automatically stores or fetches data using the
address provided by the host. The HPI DMA logic is independent of the EDMA3 controller included in the
DSP.
In the DSP system, master and slave peripherals communicate with each other via the Switched Central
Resource (SCR). By definition, master peripherals are capable of initiating read and write transfers in the
system and may not solely rely on the EDMA3 controller for their data transfers. Slave peripherals rely on
the EDMA3 controller to perform transfers. The HPI is a master peripheral; it uses its DMA logic to directly
communicate with the rest of the system via the SCR and does not rely on the EDMA3 controller for its
data transfers. Note that the HPI cannot access all DSP resources or peripherals; see the device-specific
data manual for a list of resources accessible through the HPI.
10
Host Port Interface (HPI)
Section
2.7.1).
SPRUF87A – October 2007 – Revised May 2008
www.ti.com
Submit Documentation Feedback
Advertisement
Table of Contents
