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9.2 Functional Block Diagrams
VDD (x9)
VDDO (x6)
3.3 V
3.3/2.5/1.8 V
Power Conditioning
(all blocks)
INSEL0[1:0]
IN0
IN1
IN2
IN3
IN5 (PLL2
FB CLK)
IN4 (PLL1
FB CLK)
INSEL1[1:0]
Inputs (3.3 V)
SDA
Registers
EEPROM
ROM
SCL
HW_SW_CTRL
Device Control
and Status
GPIO[6:0]
1.5-V to 3.3-V
STATUS[1:0]
Logic I/O Levels
PDN
Control (3.3 V)
9.3 Feature Description
The following section describes the features of the device functional blocks.
9.3.1 Oscillator Input (XO_P/N)
The XO input is the reference clock for the Fractional-N APLLs. The combination of XO and APLL determine the
jitter and phase noise performance of the output clocks. For optimal performance, the XO frequency should be
between 48 to 54 MHz and have a non-integer frequency relationship with the VCO frequencies so the APLLs
operate in Fractional mode.
The XO input buffer has programmable input on-chip termination and biasing controls to support any oscillator
interface type.
Copyright © 2018, Texas Instruments Incorporated
TCXO/OCXO
10-54 MHz
(Optional)
10-100 MHz
M Div
5-b
x2
System
Clocks (3.3 V)
R Div
To REF TDC
PLL Core 1
16-b
VCO1 Freq = 4.8 - 5.4 GHz
To TCXO TDC
FB Div
5-b
FB Div
5-b
To TCXO TDC
PLL Core 2
R Div
To REF TDC
VCO2 Freq = 5.5 - 6.2 GHz
16-b
Synthesizers (3.3 V)
CAP (x3) LF1
Figure 18. LMK05028 Block Diagram
Product Folder Links:
XO
0
2
1
1
2
0
3
4
5
0
To APLL
P1 Div
1
2
3
4
VCO1
5
P2 Div
0
1
2
3
/48
/48
0
1
2
3
To APLL
P1 Div
VCO2
0
1
P2 Div
2
3
P Div range:
/4-/9, /11, /13
0
1
2
3
Output (3.3/2.5/1.8 V)
LF2
Copyright © 2018, Texas Instruments Incorporated
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LMK05028
LMK05028
SNAS724 – FEBRUARY 2018
SYNC
OUT Divs
OUT0
11-b * 20-b
OUT Div
OUT1
20-b
OUT2
OUT Div
20-b
OUT3
OUT4
OUT Div
20-b
OUT5
OUT Div
OUT6
20-b
OUT Divs
OUT7
11-b * 20-b
21
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