Pin Assignments; Table 10: Pin Assignment Of Jp2 - CipherLab 5000 Hardware Manual

2.2.1 Pin Assignments

The pin assignments are listed and described below.
Pin No. Name
1 GND
2 GND
3 CTS0
4 RTS0
5 RXD0
6 TXD0
7 +5V
8 DO4_NO
9 DO4_COM
10 DO4_NC
11 DO3_NO
12 DO3_COM
13 DO3_NC
14 DO2_NO
15 DO2_COM
16 DO2_NC
17 DO1_NO
18 DO1_COM
19 DO1_NC

Table 10: Pin Assignment of JP2

Installing 5000/5100:
JP2:
Category
Power
Power
From External reader
To External reader
From External reader
To External reader
Power
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Description
Ground
Ground
CMOS-level clear to send
CMOS-level request to send
CMOS-level receive data
CMOS-level transmit data
+5V/200mA to power
devices
#4, normal open
#4, common
#4, normal close
#3, normal open
#3, common
#3, normal close
#2, normal open
#2, common
#2, normal close
#1, normal open
#1, common
#1, normal close
Wiring
external
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