Cpu; Memory & Calendar; Table 2: Memory Explained - CipherLab 5000 Hardware Manual

1.3.2 CPU

A 16-bit low power CMOS CPU is utilized. With little current consumed, yet, this CPU
can run under 22.1184MHz and provide more than 6 MIPS of computation powers.
1.3.3 Memory & Calendar
In the event of a power failure with no battery pack installed, the 7 mAh button cell on
the main board is to keep contents of the SRAM and run the calendar for at least 1
week.
An optional memory card upgrades memory to 2, 4, or 8 Mbytes SRAM with its own
contents backup button cell. The DIP switch on the card must be set ON for the cell to
work.
Program memory:
- 2 Mbytes flash memory for core, OS, application software, fonts, etc.
Data memory:
256 Kbytes SRAM with contents backup by a 7 mAh rechargeable Li button cell.
-
Calendar:
A calendar chip is also equipped for accurate time/date logging.
-
Non-stop operation is also provided through the same Li button cell for SRAM
-
contents backup.

Table 2: Memory explained

10
Introducing 5000/5100:
Features