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output - i.e. a conventional PWM approach. The current
feedback method has instantaneous response to input
voltage
variation
since lower input
automatically force the ramp waveform on R14 (from Vin
across Lpri of TX2) to be more shallow which will
instantly force a longer mosfet On-time. By contrast the
conventional PWM method would require an error in the
output voltage to occur before the mosfet ON-time could
be increased.
In addition we get pulse by pulse current limiting for free
since the chip contains a simple cct which turns the mosfet
off if the current sense input voltage exceeds 1V
irrespective of what the error amplifier is doing. Thus a
short circuit on the output of the supply will cause the
supply to power limit and the output voltages of all of the
supplies to fall which should prevent catastrophic failure.
The mosfet is driven from the output of the IC through a
22R resistor. This resistor value is chosen to be
compromise between small value for rapid turn ON and
turn -OFF of M1 and high value for soft turn ON and low
EMC.
IC2 is powered through the network R11, DZ2, C16, C17.
This network provides a 10V supply for the controller with
values calculated to maintain regulation at minimum input
line voltage (=195Vac when set to 230Vac). The IC draws
approximately 20mA in normal operation.
Network R8, C15 are feedback loop compensation
components. The connection is actually between the
internal E/A output node and the negative input of the E/A.
C13 provides decoupling for the voltage reference.
The thee main outputs (+3V3, +5V, +12V) have small
value inductors inserted in series with the outputs (L3, L4,
L5). These provide excellent attenuation of switching
voltage spikes (in combination with the following
capacitors) in an attempt to keeps the noise on the supplies
as low as possible. Similarly the series networks R15, C19
= 1K +1nF; R17, C25; R18, C30; R19, C36 are snubbing
networks which are also used to limit switching noise
spikes.
The 4V3 output is semi-regulated by the simple emitter
follower / zener network TR3, DZ3.
This arrangement reduces the output voltage variation to
well within the required range. Fuse F5 is for current
limiting because the wire on the 4V3 supply is only rated
for low currents and a short cct on this output would cause
high current to flow in the winding which would otherwise
overheat the transformer.
Output Voltage Specification
The specification for the PSU over full range of input
voltages / load currents.
Supply
tolerance
Min V
%
3V3
5
3.135
5V
5
4.75
12V
10
10.8
4V3
5
4.085
19V5
5
18.525
voltage will
Nom V
Max V
V
V
V
3.3
3.465
5
5.25
12
13.2
4.3
4.515
19.5
20.475
Voltage across C3
Nominal
Tol
V
%
V (C3)
27.5
5
Free running frequency
Nominal
Tol
%
KHz
Frequency
27
10
L878 AV Circuit
Summary
This board is used in the DV27 and DV88 DVD players. It
takes the outputs of the DSP board and produces all the
video and audio outputs of the system (the exception being
the progressive scan output on the DV27, which is on a
separate card).
The board features 2 mono DACs for stereo analogue
audio, an audio clock oscillator, data re-clocking, and
video buffers. There is also a power supply circuit for the
audio section and separate regulators for sensitive clock
supplies.
A key feature of the design is that it is 'DVD-Audio
ready'. The DACs and audio clock are capable of
supporting various sample rates up to 192kHz, and there
are expansion connectors present to allow an additional
audio DAC board to be fitted. This will handle the extra 4
channels of surround audio (This is a requirement for
DVD-Audio since no digital interface is allowed to
connect to external processors).
The DV27 and DV88 DVD-Video players can therefore be
migrated in the future to support DVD-Audio. This will be
done by replacing the existing DSP board for one that
supports DVD-audio, and adding a 2
Overview
The audio power supply circuit takes an AC feed from the
main PSU and provides DC power rails for the DACs and
output buffer stage.
The clock circuit provides a selectable clock frequency
that can be 4 different frequencies. There is a clock
distribution circuit in here that feeds clocks to the DACs,
to
the
re-clocking
circuit,
synchronisation), and to an additional DAC board (not
fitted at present).
The re-clocking circuit accepts an I2S format audio signals
from the DSP board and an SPDIF signal. These are re-
latched to the local clock to reduce jitter. The re-clocked
I2S is passed on to the DACs, and the re-clocked SPDIF
goes on to the coaxial output buffer and optical output.
The DAC circuit provides a stereo analogue audio output
on phonos, this is also connected to the SCART AV
output. The DACs are operated under software control,
this is by an SPI bus from the DSP board.
On the video side, 6 channels of analogue video are
received from the DSP board. These are filtered and
buffered before going to the outside world. The video
signals consist of composite, S-video and 3 lines that are
switchable YUV/RGB. These 3 lines go to phono
connectors (for YUV) and the SCART (for RGB). The
player setup menu has to be set appropriately for one or
the other.
The SCART output also has some status signals to control
TVs, these are generated from control lines from the DSP
board.
min
nom
max
V
V
V
26.13
27.50
28.88
Min
Nom
Max
KHz
KHz
KHz
24.30
27.00
29.70
nd
DAC board.
the
DSP
board
(for
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