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1
2
Audio clock:
FSEL1. 0
Frequency
0
11 2896MHz
1
12 288MHz
2
22 5792MHz
D
3
24 576MHz
Rev 2.1/3 0: Changed C126 from 47pF to 56pF
To slow audio clock down slightly
Z12A
R110
R75
1
2
100R 0805
22K 0805
R33
74HCU04 SM
C57
10K 0805
100N 0805
C
Z12B
R80
3
4
FSEL0
100R 0805
74HCU04 SM
B
Z12E
Z12F
11
10
13
12
74HCU04 SM
74HCU04 SM
+5V_CLOCK2
Use +5V_CLOCK1 or +5V_CLOCK2?
+5V_CLOCK1
L12
7F004
Z12G
C46
C45
A
100N 0805
100N 0805
74HCU04 SM
1
2
3
CLOCKS
sample rate
44.1K x 256
48K x 256
88 2 x 256 (or 176.4K x 128)
+5V_CLOCK1 or +5V_CLOCK2?
96K x 256 (or 192K x 128)
+5V_CLOCK1
L13
7F004
C55
100N 0805
+5V_CLOCK1
R78
C56
100R 0805
R120
100N 0805
680R 0805
C139
R14
330R 0805
24 576MHz oscillator
Q2
100P NPO 0805
BFS17H
C136
X2
24 576MHZ
220P NPO 0805
R114
C126
C138
680R 0805
100P NPO 0805
56P NPO 0805
L22
10UH SM
22.5792MHz oscillator
Q3
R111
BFS17H
22K 0805
X1
C137
R40
C58
22.5792MHZ
220P NPO 0805
10K 0805
100N 0805
R121
C127
C140
680R 0805
47P NPO 0805
100P NPO 0805
L23
10UH SM
Z10B
12
9
D
Q
Z14B
74VHC125 SM
11
CLK
5
Q 8
74VHC74MX SM
+5V_CLOCK2
L14
7F004
Z14E
Z10C
C47
C48
C49
100N 0805
100N 0805
100N 0805
74VHC74MX SM
3
4
5
C54
+5V_CLOCK2
100N 0805
Divide by 2
74AHC1GU04 SM
Z10A
R59
2
5
D
Q
Z27
100R 0805
R79
2
4
3
CLK
100R 0805
Q 6
74VHC74MX SM
R77
4M7 0805
Z12C
Z12D
5
6
9
8
FSEL1
74HCU04 SM
74HCU04 SM
+5V_CLOCK2
L15
Z21E
7F004
C59
C60
6
100N 0805
100N 0805
74VHC125 SM
74VHC125 SM
DRAWING TITLE
DVD AV PCB - Clocks
Circuit Diagram
23425
Notes:
A & R Cambridge Ltd.
Pembroke Avenue
Denny Industrial Centre
Waterbeach
Filename
Cambridge CB5 9PB
J:\Change Control\ECO AGENDA\02 E000 L878 cap voltage correction\L878 3.3A.ddb - Documents\L878C4 3.3A.sch
4
5
6
Z21A
74VHC125 SM
2
3
Z21D
74VHC125 SM
12
11
Z14C
74VHC125 SM
Z21C
R61
9
8
74VHC125 SM
100R 0805
9
8
Z14D
74VHC125 SM
12
11
Z21B
74VHC125 SM
5
6
Z14A
74VHC125 SM
2
3
02_E000 PG
07/01/02 Admin change - cap voltages corrected on BOM
PG
13/11/01 C155 changed to 100R
01_1047
PG
15-03-01 Diodes changed from 3B22D to 3BS1D
01_1000
PG
02/01/01 Change R9,R10 from 100R to 22R
00_1136
PG
24/11/00 Issue 3 PCB with 8740 DACs
ECO No.
INITIALS
DATE
Drawn by:
Date Printed
PG
7-Jan-2002
6
7
8
On issue 3 R74 changed to 33R
To re-clocking
R67
CK256FS_RCK
100R 0805
C77
22P NPO 0805
NF
D
To DACs
R62
CK256FS_DAC_L
100R 0805
C80
22P NPO 0805
NF
R74
CK256FS_DAC_R
33R 0805
C156
22P NPO 0805
NF
C
To DSP board
R63
CK256FS_DSP
33R 0805
C157
22P NPO 0805
NF
To 2nd DAC board
R64
CK256FS_EXT
33R 0805
C158
22P NPO 0805
NF
B
3.3A
A
3.3
3.2
3.1
3.0
DESCRIPTION OF CHANGE
ISSUE
Sheet
4
of
7
L878C4
DRAWING NO.
7
8
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