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2
MPGSTBY-
MPGSTBY-
MPGRST-
MPGRST-
DVDERR
DVDERR
DVDSOS
DVDSOS
DVDVALID
DVDVALID
DVDSTB
DVDSTB
DVDREQ
DVDREQ
DVDDAT[0..7]
DVDDAT[0..7]
D
GPS0 was GAIN_SCALING on isss A
CDERR
CDFRM
CDDAT
CDCLK
HD7
HD6
HD5
C
HD4
HD3
HD2
HD1
HD0
HA4
HD[0 15]
HD[0..15]
HA3
HA2
HA1
HA[1..4]
HA[1..4]
HWR-
MPGCS-
HRD-
MPGIRQ-
+3.3V
B
pin150
pin18
pin28
pin48
pin73
pin103
C57
C58
C59
C21
C22
C23
100N 0805
100N 0805
100N 0805
100N 0805
100N 0805
100N 0805
+3.3V
+3.3V
+3.3V
+
C24
+
C25
+
C26
10U EL SM
10U EL SM
10U EL SM
A
+3.3V
+3.3V
+5V
+5V
GND
1
2
3
L1
+3.3V
7F004
C15
100N 0805
DVDDAT0
DVDDAT1
DVDDAT2
DVDDAT3
C82
DVDDAT4
DVDDAT5
47N 0805
DVDDAT6
DVDDAT7
+3.3V
GND
C16
100N 0805
1
GND
2
GPSI
3
CDERR
HD15
4
CDFRM
HD14
5
CDDAT
HD13
6
CDCLK
HD12
7
HD11
8
V3.3
9
HD10
10
HD09
11
HD08
12
HD07
13
GND
14
HD06
15
HD05
16
HD04
17
HD03
18
V3.3
19
HD02
20
HD01
21
HD00
22
HA3
23
GND
24
HA2
25
HA1
26
HA0
27
HWR-
HWR
28
V3.3
29
MPGCS-
HCS
30
HRD-
HRD
31
HRDY
32
HACK
33
V3.3
34
MPGIRQ-
HIRQ
35
HWID
36
HORD
37
HTYPE
MA4
38
A4
MA3
39
A3
40
GND
C19
100N 0805
GND
+3.3V
U8
ZORANQFP160
ZR36700
+3.3V
C27
U11
100N 0805
KM416S1020BT
SDRAM 0
3
4
5
C40
Rev 2.1 - changed C40 and C52 from 22pF to 33pF
33P NPO 0805
and R36 from 100R to 0R
Y2
(corrects 27MHz frequency)
27MHZ SM
C52
R36
0R0 0805
33P NPO 0805
Rev 2.2 - deleted ENABLE_AV
(Use MPGSTBY- for SCART control instead)
GAIN_SCALING
High for HDCD gain scaling
(was 16/9 on iss A)
R10
R28
0R0 0805
100R 0805
0R0 0805
NF
R27
R11
+3.3V
GND
100R 0805
C17
100N 0805
RP4
1
8
2
7
3
6
4
5
120
GND
100R X 4 ISO
119
ABCLK
118
ALRCLK
117
SPDIF
SPDIF
116
AOUT2
AOUT2
115
AOUT1
AOUT1
114
AOUT0
AOUT0
113
V3.3
112
RP5
AIN
111
1
10
UV0/TCK
UV0
110
2
9
UV1/TDO
UV1
109
3
8
UV2/TDI
UV2
108
4
7
GND
107
5
6
UV3/TMS
UV3
106
UV4
UV4
105
RPACK SM 4K7 BUS
UV5
104
UV6
103
V3.3
102
UV7
RP6
101
PYUV0
1
8
Y0
100
PYUV1
2
7
Y1
99
3
6
PYUV2
Y2
98
4
5
V3.3
97
PYUV3
Y3
100R X 4 ISO
96
PYUV4
Y4
95
PYUV5
Y5
RP7
94
1
8
PYUV6
Y6
93
2
7
GND
92
3
6
PYUV7
Y7
91
4
5
FIELD
90
HSYNC-
HSYNC-
HSYNC
100R X 4 ISO
89
VSYNC-
VSYNC
88
VSYNC-
CBLANK
87
VDEN
86
V3.3
85
CN11
VMASTER
84
1
Sync connector for progressive scan board
VCLK
83
2
TESTMODE
82
MD0
3
MD0
81
4
GND
AMPCT4
C20
100N 0805
GND
+3.3V
+3.3V
MD[0..15]
R37
MPCLK
MDQM
33R 0805
MWE-
MCAS-
MRAS-
MCS1-
MA[0..10]
+3 3V
GND
U10
C28
C29
KM416S1020BT
100N 0805
100N 0805
GND
+3 3V
MDQM
MPCLKB
DRAWING TITLE
DSP BOARD - DVD PROC
SDRAM 1
NOT FITTED
23425
A & R Cambridge Ltd.
Pembroke Avenue
Denny Industrial Centre
Waterbeach
Cambridge CB5 9PB
4
5
6
7
+5V
C45
100N 0805
U14
1
R7
4
2
1K0 0805
74AHC1G00 SM
R1
CLK27PS
75R 0805
R3
Q_49
CLK27
75R 0805
AMCLK
AMCLK is now an INPUT
It may be an output when testing
ABCLK
ALRCLK
SPDIF-I34
ASDAT2
ASDAT1
ASDAT0
PCB Note:
Keep damping resistors
close to U8
YUV[0..7]
YUV[0..7]
YUV0
YUV1
YUV2
YUV3
YUV4
YUV5
YUV6
YUV7
MD[0..15]
MA[0..10]
ZR36700 Notes:
Video Sync Master mode (36700 drives HSYNC-, VSYNC-)
C30
In 8-bit pixel bus mode, UV[7..5] are not used; UV[4..0]
100N 0805
are possible inputs from an external OSD device.
MD[0..15]
Circuit Diagram
Notes:
01_1139
CL
08/08/01
ECO No.
INITIALS
DATE
Filename
Date Printed
J \Change Control\ECO AGENDA\01 1139 L875PB MODS cliff\L875 4.0.ddb - Documents\ 875C3 4 0 SCH
5-Sep-2001
6
7
8
Wordclock to synchronise PSU
LRCK_PSU
D
C
B
A
REMOVED CN2 & CN3, PCB WIDTH CHANGED
4.0
DESCRIPTION OF CHANGE
ISSUE
Drawn by
Sheet
3
of
5
L875C3
PG
DRAWING NO.
8
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