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1
2
DAC
NRESET
NRESET
MD
MD
MC
MC
ML8716
ML_8716_L
D
LRCK_DAC_L
LRCK_DAC_L
AD_DAC_L
AD_DAC_L
BCK_DAC_L
BCK_DAC_L
CK256FS_DAC_L
CK256FS DAC L
L9
+ C76
33UH SM
C61
10U EL SG
10N 0805
R8110R SM
+5V_DAC_L
+5V_DAC_L
+ C142
10U SILMIC
+ C78
C70
10U EL SG
1N0 PP
C
LRCK_DAC_R
LRCK_DAC_R
AD_DAC_R
AD_DAC_R
BCK_DAC_R
BCK DAC R
CK256FS_DAC_R
CK256FS_DAC_R
B
L10
+ C79
33UH SM
C62
10U EL SG
10N 0805
R82
+5V_DAC_R
10R 0805
+5V_DAC_R
+ C141
10U SILMIC
+ C81
C72
10U EL SG
1N0 PP
A
1
2
3
DACs operate in mono differen ial mode
Control is via SPI bus
Different LOAD signals are required because 1 is configured as LEFT
and one as RIGHT
2nd DAC board has its own LOAD signal
because DACs there are in stereo mode
LEFT DAC
Z17
WM8740
1
28
LRCIN
ML/IIS
2
27
DIN
MC/DM1
3
26
BCKIN
MD/DM0
4
25
MODE8X
MUTE
5
24
SCLK
MODE
6
23
DIFFHW
CS/IWO
7
RST 22
DGND
8
21
DVDD
ZERO
9
20
AVDDR
AVDDL
10
AGND2L 19
AGND2R
11
18
VMIDR
VMIDL
12
17
VOUTRN
VOUTLN
13
16
VOUTRP
VOUTLP
14
15
AGND1
Vcc
C69
1N0 PP
WM8740
ML_8716_R
RIGHT DAC
Z18
WM8740
1
28
LRCIN
ML/IIS
2
27
MC
DIN
MC/DM1
3
26
MD
BCKIN
MD/DM0
4
25
MODE8X
MUTE
5
MODE 24
SCLK
6
23
DIFFHW
CS/IWO
7
22
NRESET
DGND
RST
8
21
DVDD
ZERO
9
20
AVDDR
AVDDL
10
19
AGND2R
AGND2L
11
18
VMIDR
VMIDL
12
17
VOUTRN
VOUTLN
13
VOUTLP 16
VOUTRP
14
15
AGND1
Vcc
C73
WM8740
1N0 PP
3
4
5
MPORTANT NOTE:
Issue 3 board uses WM8740 DACs
Issue 2 and earlier use WM8716 DACs
Also, values of R83,R84,R87,R88 are different
2nd order Butterworth LPF
R123
with differen ial i/p
Fc=50K, Av=1
22K 0805
R84
R92
22K 0805
3K3 0805
C82
R86
C87
Z19A
1N0 PP
12K 0805
220P PP
3
1
2
R124
OPA2134PA SM
22K 0805
C86
R83
R91
22K 0805
3K3 0805
220P PP
R85
C83
1N0 PP
12K 0805
High for HDCD
GAIN
R112
C147
10K 0805
NF
1N 0805
-12VA
Butterwor h LPF
R125
with differen ial i/p
Fc=50K, Av=1
22K 0805
R88
R94
22K 0805
3K3 0805
C84
R90
C89
Z20A
1N0 PP
220P PP
12K 0805
3
1
2
R126
OPA2134PA SM
22K 0805
C88
R87
R93
22K 0805
3K3 0805
220P PP
R89
C85
1N0 PP
12K 0805
+12VA
Z19C
C63
Z20C
C65
1N 0805
1N 0805
OPA2134PA SM
OPA2134PA SM
C64
C66
1N 0805
1N 0805
-12VA
DRAWING TITLE
DVD AV PCB - DACs
Circuit Diagram
23425
Notes:
A & R Cambridge Ltd.
Pembroke Avenue
Denny Industrial Centre
Waterbeach
Filename
Cambridge CB5 9PB
J:\Change Control\ECO AGENDA\02 E000 L878 cap voltage correction\L878 3.3A.ddb - Documents\L878C5 3.3A.sch
4
5
6
7
Signal phase is preserved at o/p
Gain of -2 for HDCD
O herwise -1
R19
Z19B
OPA2134PA SM
5
C90
1K 0805
R101
7
R95
6
75R 0805
100U CERAFINE
2K2 0805
R37
R96
R97
10K 0805
2K2 0805
2K2 0805
Switch is ON for HDCD
Z11
+12VA
Q_30
1
16
SEL1
SEL2
QPAD
2
15
D1
D2
C148
3
14
1N 0805
S1
S2
Q_31
4
13
right_out
V-
V+
QPAD
5
VL 12
+5V_DAC_L
GND
6
11
S4
S3
7
10
C149
D4
D3
1N 0805
8
SEL3 9
SEL4
DG413DY
Signal phase is preserved at o/p
Gain of -2 for HDCD
O herwise -1
R20
Z20B
OPA2134PA SM
5
C91
1K 0805
R102
7
R98
6
75R 0805
100U CERAFINE
2K2 0805
R38
R99
R100
10K 0805
2K2 0805
2K2 0805
+ C15
22U EL
+ C16
22U EL
02_E000 PG
07/01/02 Admin change - cap voltages corrected on BOM
01_1047
PG
13/11/01 C155 changed to 100R
01_1000
PG
15-03-01 Diodes changed from 3B22D to 3BS1D
00_1136
PG
02/01/01 Change R9,R10 from 100R to 22R
00_1072
PG
24/11/00 Issue 3 PCB with 8740 DACs
ECO No.
INITIALS
DATE
Drawn by:
Date Printed
PG
7-Jan-2002
6
7
8
R5
D
SCART_L
1K 0805
left_out
RLY2A
RLY DPDT SM
EMCGND
SK6B
SK6A
left_out
1
F
F
C
EMC
N
N
C50
PHONO4G
PHONO4G
1N 0805
Q_32
OPGND
QPAD
L16
7F004
R6
SCART R
1K 0805
right_out
B
RLY2B
RLY DPDT SM
3.3A
A
3.3
3.2
3.1
3.0
DESCRIPTION OF CHANGE
ISSUE
Sheet
5
of
7
L878C5
DRAWING NO.
8
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