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1
2
D
RESET-
MPGCS-
MPGIRQ-
DRVIRQ-
IRIRQ-
SCL
SCL
SDA
SDA
U2
C86
1
8
A0
VDD
+5V
100N 0805
2
7
A1
WP
3
6
A2
SCL
4
5
VSS
SDA
24LC256 SM
+5V
4K7 0805
R6
SSC-ATN-
MUTE
C
C2
C3
22P NPO 0805
22P NPO 0805
FPDIN
FPSEL
Y1
FPCLK
FPDOUT
16MHZ SM
R5
100R 0805
+5V
MPGRST- is low after
R61
reset.
MPGRST- must be set high
R63
FPDIN
to access MPEG chip.
FPSEL
FPCLK
4K7 0805
FPDOUT
MPGRST-
MPGSTBY-
SSC-MRST
SSC-MTSR
TXD
RXD
SSC-MRST
HWRH-
SSC-MTSR
SSC-SCLK
SSC-SCLK
HA16
HA17
HA18
HA19
TXD
RXD
B
Resistor on TXD line added on rev 3.0
R35
R38
For static protection
10K 0805
4K7 0805
C9
100N 0805
FSEL0
FSEL1
HD9,10 removed for iss B
A
HA[1..19]
+5V
+5V
GND
1
2
3
U1
DS1233
1
Gnd
RESET-
4
Gnd
2
MPGCS-
Res
3
MPGIRQ-
Vcc
+5V
DS1233 SM
C1
DRV RQ-
1N 0805
RIRQ-
EEPROM is now 32K x 8
CS_EXT
R4
+5V
4K7 0805
RAMCS-
ROMCS-
+5V
P5.14-15 is read-only inp
RP1
1
10
2
9
3
8
HD13
4
7
HD14
5
6
+5V
RPACK SM 4K7 BUS
C161-P80
NMI-
+5V
+5V
+5V
GND
C4
HA15
100N 0805
HA14
C5
100N 0805
HA15
HA14
1
60
HA13
Vss
A13
2
59
HA12
XTAL1
A12
3
58
HA11
XTAL2
A11
4
57
HA10
Vcc
A10
5
56
HA9
P3.2/CAPIN
A9
6
55
HA8
P3.3/T3OUT
A8
7
54
HA7
P3.4.T3EUD
U3
A7
8
53
HA6
P3.5/T4IN
A6
9
C1610
52
HA5
P3.6/T3IN
A5
10
51
HA4
P3.7/T2IN
A4
11
50
HA3
P3.8/MRST
A3
12
49
HA2
P3.9/MTSR
A2
13
48
HA1
P3.10/TxD0
A1
14
47
P3.11/RxD0
A0
15
46
HD15
P3.12/BHE/WRH
AD15
16
45
HD14
P3.13/SCLK
AD14
17
44
HD13
P4.0/A16
AD13
18
43
HD12
P4.1/A17
AD12
19
42
HD11
P4.2/A18
AD11
20
41
HD10
P4.3/A19
AD10
C10
100N 0805
GND
GND
+5V
+5V
HD9
HD8
HD7
HD6
HD5
HD4
HD3
HD2
HD1
HALE
HD0
HWR-
HRD-
HWRH-
HD[0..15]
RP2
RP3
+5V
1
10
1
10
HD6
HD3
2
9
2
9
HD15
HD2
HD4
3
8
3
8
HD8
HD1
HD5
4
7
4
7
HD12
HD0
HD7
5
6
5
6
HD11
+5V
RPACK SM 4K7 BUS
RPACK SM 4K7 BUS
HD[0..15]
HA[1..19]
3
4
5
HA[1..19]
HA[1..19]
PROM Configuration Note:
Depth/Width ROM-P1
256Kx16
N/C
512Kx16
A18
R2
HA19
ROM-P1
0R0 0805
RAMCS-
ROMCS-
HD[0..15]
U5
12
13
HA1
HD8
A0
D0
11
14
HA2
HD9
A1
D1
10
15
HA3
HD10
A2
D2
9
17
HA4
HD11
A3
D3
HA5
8
18
HD12
A4
D4
HA6
7
19
HD13
A5
D5
HA7
6
20
HD14
A6
D6
HA8
5
21
HD15
A7
D7
HA9
27
A8
HA10
26
A9
23
HA11
A10
25
22
HA12
ROMCS-
A11
CE
4
24
HA13
HRD-
A12
OE
28
31
HA14
HWRH-
A13
WE/PGM
29
HA15
A14
3
32
HA16
A15
VCC
+5V
2
HA17
A16
30
C6
HA18
A17
1
16
100N 0805
A18/VPP
GND
ROM PLCC
PLCC-32-SMT
ROM-P1
U4
HA1
12
13
HD0
A0
D0
HA2
11
14
HD1
A1
D1
HA3
10
15
HD2
A2
D2
9
17
HA4
HD3
A3
D3
8
18
HA5
HD4
A4
D4
7
19
HA6
HD5
A5
D5
6
20
HA7
HD6
A6
D6
5
21
HA8
HD7
A7
D7
27
HA9
A8
26
HA10
A9
23
HA11
A10
25
22
HA12
ROMCS-
A11
CE
4
24
HA13
HRD-
A12
OE
28
31
HA14
HWR-
A13
WE/PGM
29
HA15
A14
3
32
HA16
A15
VCC
+5V
HA17
2
A16
C8
HA18
30
A17
100N 0805
1
16
A18/VPP
GND
ROM PLCC
PLCC-32-SMT
ROM-P1
PCB Note:
Provide clearance around PROM
for SMT Sockets
HD[0..15]
HWR-
HRD-
HWRH-
C1610 Configuration Note:
HD6 = 0 Demultiplexed Bus
HD7 = 1 16-bit Data Bus
HD8 = 0 WRH- and WRL- control
HD[12:11] = 00b 1Mbyte segment length (A0...A19)
HD15 = 0 CLK divide by 1
HD[9:10]=00b CS3 is GPIO(HRST)
DRAWING TITLE
DSP BOARD CPU
23425
A & R Cambridge Ltd.
Pembroke Avenue
Denny Industrial Centre
Waterbeach
Cambridge CB5 9PB
4
5
6
7
NF
R12
R13
HA17
+5V
0R0 0805
0R0 0805
RAM-P30
RAM Configuration Note:
Device RAM-P12 RAM-P30
Depth
(A0)
(A17)
/Width
128Kx16: HA17
VCC
(Default)
512Kx16: HA19
HA17
NF
R14
R15
HA17
0R0 0805
0R0 0805
HA19
RAM-P12
HA[1..4]
HA[1..4]
HA1
HA1
HA2
HA2
HA3
HA3
HA4
HA4
HD[0..15]
RAM-P12
U7
12
13
HD8
A0
D0
11
14
HA1
HD9
A1
D1
10
15
HA2
HD10
A2
D2
9
17
HA3
HD11
A3
D3
HA4
8
18
HD12
A4
D4
HA5
7
19
HD13
A5
D5
HA6
6
20
HD14
A6
D6
HA7
5
21
HD15
A7
D7
HA8
27
A8
HA9
26
U12A
A9
23
HD8
3
2
HA10
A10
D0
Q0
25
HD9
4
5
HA11
A11
D1
Q1
4
HD10
7
6
HA12
A12
D2
Q2
28
HD11
8
9
HA13
A13
D3
Q3
3
HD12
13
12
HA14
A14
D4
Q4
31
HD13
14
15
HA15
A15
D5
Q5
2
+5V
HD14
17
16
HA16
A16
D6
Q6
30
HD15
18
19
RAM-P30
A17
D7
Q7
32
VCC
1
11
1
HA18
A18
CLK
OE
22
C7
74HC374 SM
RAMCS-
CE
24
100N 0805
HRD-
RD
29
16
HWRH-
WR
GND
SRAM
SOJ-32-300-400
RAM-P12
U6
12
13
HD0
A0
D0
HA1
11
14
HD1
A1
D1
10
15
HA2
HD2
A2
D2
9
17
HA3
HD3
A3
D3
8
18
HA4
HD4
A4
D4
7
19
HA5
HD5
A5
D5
6
20
HA6
HD6
A6
D6
5
21
HA7
HD7
A7
D7
27
HA8
A8
26
HA9
A9
23
HA10
A10
25
HA11
A11
4
HA12
A12
28
HA13
A13
3
HA14
A14
HA15
31
A15
HA16
2
+5V
A16
RAM-P30
30
A17
32
VCC
HA18
1
PCB Note:
A18
Stretch RAM pads to
C11
RAMCS-
22
CE
accomodate both 300mil
24
100N 0805
HRD-
RD
and 400mil wide devices.
29
16
HWR-
WR
GND
SRAM
SOJ-32-300-400
HD[0..15]
HWR-
HRD-
+5V
+5V
+5V
+
C12
+
C13
+
C14
10U EL SM
10U EL SM
10U EL SM
Circuit Diagram
Notes:
01_1139
CL
08/08/01
REMOVED CN2 & CN3, PCB WIDTH CHANGED
ECO No.
INITIALS
DATE
Drawn by
Filename
Date Printed
PG
J \Change Control\ECO AGENDA\01 1139 L875PB MODS cliff\L875 4.0.ddb - Documents\ 875C2 4 0 SCH
5-Sep-2001
6
7
8
D
C
5 wire serial I/F
MD
(controls 3 DACs)
MC
ML_8716_L
ML_8716_R
ML_8716_X
Drive reset
HRST
Control for SCART
16/9
+5V
U12B
C39
100N 0805
74HC374 SM
B
A
4.0
DESCRIPTION OF CHANGE
ISSUE
Sheet
2
of
5
L875C2
DRAWING NO.
8
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