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The ZR36701 acts as a bridge between the SSC and AV
interfaces on one side, and the ATAPI drive on the other.
The ATAPI interface of the chip connects to the DVD
drive via 40 way IDC connector CN10.
Signal descriptions:
ATCRESET-Active low reset generated by ZR36701 to
ATAPI drive
DD[0..15] Bidirectional data bus
DA[0..2] Address lines - output from ZR36701
CS0-,CS1- Chip selects - output from ZR36701 –
make up part of ATAPI address
INTRQ
Interrupt request from drive to ZR36701
DIOW-
Write strobe - output from ZR36701
DIOR-
Read strobe - output from ZR36701
IORDY
Device ready signal from drive
Board Specifications
Power Supply:
+5V +/- 5% at 280mA nominal
3.3V +/-5% at 400mA nominal.
Video output levels:
Composite: 700mV nominal (in PAL) black-peak white
into 75R
S-Video: Y 700mV nominal (in PAL) black-peak white (in
PAL) into 75R
S-Sideo: C 885mV pk-pk nominal (in PAL) into 75R
Component Y: 700mV nominal (in PAL) black to peak
white into 75R.
Component U: 700mV pk-pk nominal for 100% colour
bars, into 75R.
Component V: 700mV pk-pk nominal for 100% colour
bars, into 75R.
L877 Circuit
The PSU consists of 4 function blocks.
These are :
1.
Mains to DC block
2.
-19V5 supply.
3.
PSU Sync Cicuit.
4.
Switch Mode PSU .
The Mains to DC Block.
The mains to DC Block provides an unregulated Isolated
DC Voltage from the mains supply.
The Mains Transformer TX1 (which is now toroidal - for
reduced induced hum) has dual 115V primaries which are
connected in series for 230V operation and in parallel for
115 V operation by the rear panel operated slide switch
SW2. F1 and F2 provide fusing for each primary winding
and the switching is arranged to obviate the requirement
for different fuses for 115V and 230V operation. For a
given output power the current requirements for 115V
operation are twice that for 230V operation. This
requirements is met by having the fuses in parallel for
115V operation and having only F2 in circuit for 230V
operation.
The VDRs (Voltage Dependent Resistors) VDR1 and
VDR2 ensure that the fuses will blow in the event of the
rear panel switch being set for 115V and 230V being
applied. It is likely that the VDRs will fail short in such
circumstances and will then also require replacement.
C1 and C2 are Y capacitors which form an EMC
suppression network to common mode signals with
common mode choke L1. Connector SK6 provides
connection for the analogue windings to the AV PCB. SK7
optionally allows a further transformer to be added to
provide the analogue supply in a more expensive model. In
such a model SK6 will then not be used and the additional
transformer secondary will be plugged directly into the
AV PCB.
The mains transformer TX1 is specified to provide 25V
DC at 195V Input and maximum load across C3 and give
+/- 14.5V DC with 200mA on each rail when rectified on
The AV PCB.
The main DC supply (-38V_UR) is formed by DBR1 and
C3. L2 and C4 provide EMC suppression to prevent the
current pulses drawn by the switching supply from
generating EMC interference via the mains lead
(Conducted emissions).
Note that the main DC supply -38V is a negative supply.
This allows the -19V5 supply for the display to be
generated from it and allows the switching PSU to have a
beneficial topology.
The mains transformer is designed to blow input fuses F1
and F2 in the event of a short across the main output and
the analogue supply to the AV_PCB is fused on the
AV_PCB.
The -19V5 supply
This is simply formed by and emitter follower TR1 and
zener diode DZ1. R1 provides a couple of milliamps
through DZ1. DZ1 then forms a 20V reference voltage
which biases TR1 base thereby fixing TR1 emitter 0.6V
above it to provide around -19.4V. C8 provides some noise
filtering.
PSU Sync Circuit.
The PSU is required to be synchronised to a 32KHz,
44KHz, 48KHz and 96KHz clocks.
The sync cct provides a divide by 2cct for the 96KHz
signal. The supply is then fed with a 32KHz, 44KHz and
48KHz clock.
The sync cct is formed around the non-retriggerable
monostable IC1. IC1A is set to have a time constant of
which slightly exceeds the period of the fastest allowable
clock (48KHz)
and thus if a slower clock is applied the output appearing
on Q is simply the input pulse train. A faster pulse train
has every other leading edge inhibited since the non-
retrigger time exceeds the period. Thus the divide by two
occurs. The second non-retriggerable produces a pulse of
near fixed duration. The width of the pulse was set to
move the falling edge of the sync pulse away from the
falling edge of the gate drive signal in the Switching PSU.
In this way the noise glitches associated with the falling
edge of the sync pulse do not cause mistriggering of the
PWM in the switching PSU. The Q output (pin 5) of IC1 is
a square wave signal. This is coupled and level shifted by
differentiating network C12 and R4 to the -38V rail. The
time constant C12, R4 is chosen so that only the rising and
falling edges of the output of IC1 appears across R4 as
positive and negative going spikes. The positive going
spike is added to the oscillator ramp by D3.
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