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Switch Mode PSU.
The PSU is formed around IC2 and TX2. The topology is
uncommon but it is basically a flyback supply with the
added complication that the primary of the transformer is
made to provide the +12V supply during the off time of
the mosfet. In this way the efficiency of the supply is
extremely high since all of the energy stored in the
transformer leakage inductance which is normally clamped
and dissipated is dumped into the 12V supply and used to
power the DVD. Hence the strange arrangement of the -
38V rail etc.
Control chip IC2 provides gate drive to M1. This power
mosfet connects the primary of TX1 across the -38V
supply. Note that the primary is shown on the circuit
diagram as two windings connected in series. The series
arrangement is to minimise leakage inductance and to do
this one of the windings is wound on the TX first, then the
secondaries are wound on and then the other primary is
then wound on last. This arrangement of windings where
the secondaries are sandwiched between two half
primaries significantly reduces the undesirable leakage
inductance.
The primary can thus be considered to be a single winding
which starts on pin 6 and ends on pin 3.
When this winding is applied across the supply the current
ramps up at a rate given by Vpri/Lpri amps per second.
Because of the polarity of the transformer windings all of
the secondary side diodes D5, D6, D7 and the +12V diode
D4 will be reverse biased. At some point the control cct
will decide to turn off the mosfet. When an inductor (in
this case the primary of TX1) has been charged up. (I.e.
the current has ramped up to some value or other and the
flux density has increased) then when the flow of current
is interrupted by the mosfet the voltage across the winding
reverses so as to allow the flux to return to decay.
When the voltage across the primary winding reverses the
diodes to the outputs are all forward biased and the current
which was stored in the primary ramps down into the
output capacitors through the coupled secondary windings.
At this point the drain of the power mosfet M1 which had
previously been near -38V will fly back above the DGND
0V net. The transformer is designed so that when the 5V
and 3V3 outputs are at their nominal voltage then the
mosfet drain and primary will fly around 13V above
DGND and so produce around 12V after the forward drop
of D4 across C21. At the end of the switching cycle this
behaviour is repeated.
The
apparently
complicated
secondaries for the +3V3 and +5V windings is due to the
fact that the +3V3 output is derived from a tap on the 5V
winding. The 3V3 winding thus has both of the +5V and
+3vV3 output current flowing in it. For this reason it needs
to be rated for a much higher current. The +3V3 winding
part is thus composed of two winding in parallel as shown
in the schematic symbol. The winding which produces the
4V3 output is a floating winding. Whereas the +3V3, +5V
and +12V are all develop with respect to DGND.
The switching frequency is dictated by an RC network R9,
C14, R10. These components combine with an internal
oscillator circuit which function as follows. The voltage
reference VREF produces a steady 5V reference. C14
charges through R9 (neglecting the presence of R10
temporarily). When the voltage on the RC pin (pin4)
exceeds a threshold then a mosfet internal to IC2 shorts
C14 and the cycle is repeated. In this way a ramp
waveform appears on the RC pin at the switching
frequency of the PSU. When the Voltage on C10 exceeds
the RC threshold the cap is discharged and the cycle
arrangements
of
the
begins and the PSU switching mosfet is turned ON. The
function of R10 is to allow an externally applied spike to
be superimposed on the RC pin voltage. The external spike
is generated by the sync cct. By adding a spike of a few
hundred millivolt amplitude to the RC ramp the circuit can
be forced to begin a new cycle at the instant of the spike
since this pushes the RC ramp voltage above the required
threshold.
If the spike is added at a fixed frequency the PSU will be
effectively synchronised to this externally applied clock -
as required.
The oscillator is set to free run at a frequency below the
minimum sync frequency. In this system the free running
frequency is set to around 25KHz. The minimum sync
frequency being 32KHz and maximum frequency is
48KHz. Component tolerances will give a spread of free
running frequency but the upper limit with all tolerances
stacked worst case will be less than 32KHz.
As described the RC ramp switches the power mosfet ON
at the beginning of each switch cycle. The mechanism
which switches it OFF again near the middle of the cycle -
and thus sets the switching mosfet pulse width will now be
described.
The about voltage is controlled by varying the pulse width.
In this design both the +3V3 and +5V supplies are
monitored. This is because in a multiple output switch
mode supply only the controlled output is accurately
maintained at the correct voltage (with a tolerance of
around 1%). The uncontrolled outputs may vary by around
+8% max over full line and load variation.
In this design both the +3V3 and +5V outputs are required
to have good regulation (<5%) so the feedback is arranged
so that rather than having say +5V at 1% and +3V3 at say
8% we actually end up with +3V3 and +5V at around 3%
tolerance. In fact the control loops is actually monitoring
the average voltage on +3V3 and +5V and regulating this.
The voltage of both supplies is monitored by transistor
TR2. The collector current of which is equal to the emitter
current as set by R5, R6 (neglecting base current). The
emitter resistors are scaled so that each monitored output
contributes 50% of the emitter current to TR2.
In IC2 an internal error amplifier has its positive input tied
to a 2V5 reference. The negative input of this error
amplifier is connected across series network R7, R22
which monitors the collector current of TR2. The error
amplifier changes the pulse width of the PSU by swinging
its output. In the general style of feedback systems the
error amplifier swings its output to make the voltage
difference between its inputs = zero. I.e. the voltage on the
VFB (pin 2) of IC2 is maintained at 2.5V which in turn
sets the current through R22+R7 which in turn sets the
output voltages on +3V3 and +5V.
Internal to IC2 the output of the voltage error amplifier is
actually compared with the output of another amplifier
which looks across primary current sense resistor R14. The
voltage across R14 is filtered by network R13, C18 to
remove the narrow leading edge spike caused by the
leakage inductance of TX2. When the voltage at the output
of the current sense amplifier exceeds the voltage at the
output of the voltage error amplifier then the power mosfet
is switched off. This will be around 1/3 duty cycle for an
input voltage of 36V on C4.
This mode of operation is called current mode control and
has a number of advantages over the more obvious PWM
method of comparing the output of the voltage error
amplifier with a ramp waveform and switching the mosfet
off when the ramp voltage exceeds the voltage on the E/A
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